The configuration space provides the ability to configure the core for various use cases.
The integrated AMD UltraScale™ CMAC IP makes use of a dynamic reconfiguration port (DRP) to provide the ability to configure aspects of the core without the need for fabric logic connections. In this case those configuration bits in the soft AXI Control register set will become RESERVED (unused) and the software should use the DRP operation registers to configure those attributes of the core. See
Table: DRP Map of the CMAC Block
for the DRP address map.
Table 5-5:
Configuration Register Map
|
Address
|
Register Name
|
|
0x0000
|
GT_RESET_REG
|
|
0x0004
|
RESET_REG
|
|
0x0008
|
SWITCH_CORE_MODE_REG
|
|
0x000C
|
CONFIGURATION_TX_REG1
|
|
0x0010
|
Reserved
|
|
0x0014
|
CONFIGURATION_RX_REG1
|
|
0x0018–0x001C
|
Reserved
|
|
0x0020
|
CORE_MODE_REG
|
|
0x0024
|
CORE_VERSION_REG
|
|
0x0028
|
Reserved
|
|
0x002C
|
CONFIGURATION_TX_BIP_OVERRIDE
|
|
0x0030
|
CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1
|
|
0x0034
|
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1
|
|
0x0038
|
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2
|
|
0x003C
|
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3
|
|
0x0040
|
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4
|
|
0x0044
|
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5
|
|
0x0048
|
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1
|
|
0x004C
|
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2
|
|
0x0050
|
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3
|
|
0x0054
|
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4
|
|
0x0058
|
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5
|
|
0x005C–0x0080
|
Reserved
|
|
0x0084
|
CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1
|
|
0x0088
|
CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2
|
|
0x008C
|
Reserved
|
|
0x0090
|
GT_LOOPBACK_REG
|
|
0x0094–0x009C
|
Reserved
|
|
0x00A0
|
CONFIGURATION_AN_CONTROL_REG1
|
|
0x00A4
|
CONFIGURATION_AN_CONTROL_REG2
|
|
0x00A8
|
CONFIGURATION_AN_ABILITY
|
|
0x00AC
|
CONFIGURATION_LT_CONTROL_REG1
|
|
0x00B0
|
CONFIGURATION_LT_TRAINED_REG
|
|
0x00B4
|
CONFIGURATION_LT_PRESET_REG
|
|
0x00B8
|
CONFIGURATION_LT_INIT_REG
|
|
0x00BC
|
CONFIGURATION_LT_SEED_REG0
|
|
0x00C0
|
CONFIGURATION_LT_SEED_REG1
|
|
0x00C4
|
CONFIGURATION_LT_COEFFICIENT_REG0
|
|
0x00C8
|
CONFIGURATION_LT_COEFFICIENT_REG1
|
|
0x00CC
|
USER_REG0
|
|
0x00D0–0x01FF
|
Reserved
|