DRP Address Map of the CMAC Block - 2.6 English

UltraScale Devices Integrated 100G Ethernet Subsystem Product Guide (PG165)

Document ID
PG165
Release Date
2023-06-15
Version
2.6 English

Table: DRP Map of the CMAC Block lists the DRP map of the CMAC block sorted by address.

Table 3-7: DRP Map of the CMAC Block

DRP Address (Hex)

DRP Bits

R/W

Attribute Name

Attribute Encoding (Hex)

DRP Encoding (Hex)

0

0

R/W

CTL_TX_PTP_1STEP_ENABLE

FALSE

0

TRUE

1

1

0

R/W

CTL_TX_IGNORE_FCS

FALSE

0

TRUE

1

2

0

R/W

CTL_TX_FCS_INS_ENABLE

FALSE

0

TRUE

1

8

[15:0]

R/W

CTL_TX_OPCODE_GPP[15:0]

0-FFFF

0-FFFF

9

[15:0]

R/W

CTL_TX_ETHERTYPE_PPP[15:0]]

0-FFFF

0-FFFF

A

[15:0]

R/W

CTL_TX_OPCODE_PPP[15:0]

0-FFFF

0-FFFF

10

[15:0]

R/W

CTL_TX_VL_LENGTH_MINUS1[15:0]

0-FFFF

0-FFFF

18

[15:0]

R/W

CTL_TX_SA_GPP[15:0]

0-FFFF

0-FFFF

19

[15:0]

R/W

CTL_TX_SA_GPP[31:16]

0-FFFF

0-FFFF

1A

[15:0]

R/W

CTL_TX_SA_GPP[47:32]

0-FFFF

0-FFFF

20

[15:0]

R/W

CTL_TX_DA_PPP[15:0]

0-FFFF

0-FFFF

21

[15:0]

R/W

CTL_TX_DA_PPP[31:16]

0-FFFF

0-FFFF

22

[15:0]

R/W

CTL_TX_DA_PPP[47:32]

0-FFFF

0-FFFF

28

[15:0]

R/W

CTL_TX_SA_PPP[15:0]

0-FFFF

0-FFFF

29

[15:0]

R/W

CTL_TX_SA_PPP[31:16]

0-FFFF

0-FFFF

2A

[15:0]

R/W

CTL_TX_SA_PPP[47:32]

0-FFFF

0-FFFF

30

[15:0]

R/W

CTL_TX_DA_GPP[15:0]

0-FFFF

0-FFFF

31

[15:0]

R/W

CTL_TX_DA_GPP[31:16]

0-FFFF

0-FFFF

32

[15:0]

R/W

CTL_TX_DA_GPP[47:32]

0-FFFF

0-FFFF

38

[15:0]

R/W

CTL_TX_VL_MARKER_ID0[15:0]

0-FFFF

0-FFFF

39

[15:0]

R/W

CTL_TX_VL_MARKER_ID0[31:16]

0-FFFF

0-FFFF

3A

[15:0]

R/W

CTL_TX_VL_MARKER_ID0[47:32]

0-FFFF

0-FFFF

3B

[15:0]

R/W

CTL_TX_VL_MARKER_ID0[63:48]

0-FFFF

0-FFFF

40

[15:0]

R/W

CTL_TX_VL_MARKER_ID1[15:0]

0-FFFF

0-FFFF

41

[15:0]

R/W

CTL_TX_VL_MARKER_ID1[31:16]

0-FFFF

0-FFFF

42

[15:0]

R/W

CTL_TX_VL_MARKER_ID1[47:32]

0-FFFF

0-FFFF

43

[15:0]

R/W

CTL_TX_VL_MARKER_ID1[63:48]

0-FFFF

0-FFFF

48

[15:0]

R/W

CTL_TX_VL_MARKER_ID2[15:0]

0-FFFF

0-FFFF

49

[15:0]

R/W

CTL_TX_VL_MARKER_ID2[31:16]

0-FFFF

0-FFFF

4A

[15:0]

R/W

CTL_TX_VL_MARKER_ID2[47:32]

0-FFFF

0-FFFF

4B

[15:0]

R/W

CTL_TX_VL_MARKER_ID2[63:48]

0-FFFF

0-FFFF

50

[15:0]

R/W

CTL_TX_VL_MARKER_ID3[15:0]

0-FFFF

0-FFFF

51

[15:0]

R/W

CTL_TX_VL_MARKER_ID3[31:16]

0-FFFF

0-FFFF

52

[15:0]

R/W

CTL_TX_VL_MARKER_ID3[47:32]

0-FFFF

0-FFFF

53

[15:0]

R/W

CTL_TX_VL_MARKER_ID3[63:48]

0-FFFF

0-FFFF

58

[15:0]

R/W

CTL_TX_VL_MARKER_ID4[15:0]

0-FFFF

0-FFFF

59

[15:0]

R/W

CTL_TX_VL_MARKER_ID4[31:16]

0-FFFF

0-FFFF

5A

[15:0]

R/W

CTL_TX_VL_MARKER_ID4[47:32]

0-FFFF

0-FFFF

5B

[15:0]

R/W

CTL_TX_VL_MARKER_ID4[63:48]

0-FFFF

0-FFFF

60

[15:0]

R/W

CTL_TX_VL_MARKER_ID5[15:0]

0-FFFF

0-FFFF

61

[15:0]

R/W

CTL_TX_VL_MARKER_ID5[31:16]

0-FFFF

0-FFFF

62

[15:0]

R/W

CTL_TX_VL_MARKER_ID5[47:32]

0-FFFF

0-FFFF

63

[15:0]

R/W

CTL_TX_VL_MARKER_ID5[63:48]

0-FFFF

0-FFFF

68

[15:0]

R/W

CTL_TX_VL_MARKER_ID6[15:0]

0-FFFF

0-FFFF

69

[15:0]

R/W

CTL_TX_VL_MARKER_ID6[31:16]

0-FFFF

0-FFFF

6A

[15:0]

R/W

CTL_TX_VL_MARKER_ID6[47:32]

0-FFFF

0-FFFF

6B

[15:0]

R/W

CTL_TX_VL_MARKER_ID6[63:48]

0-FFFF

0-FFFF

70

[15:0]

R/W

CTL_TX_VL_MARKER_ID7[15:0]

0-FFFF

0-FFFF

71

[15:0]

R/W

CTL_TX_VL_MARKER_ID7[31:16]

0-FFFF

0-FFFF

72

[15:0]

R/W

CTL_TX_VL_MARKER_ID7[47:32]

0-FFFF

0-FFFF

73

[15:0]

R/W

CTL_TX_VL_MARKER_ID7[63:48]

0-FFFF

0-FFFF

78

[15:0]

R/W

CTL_TX_VL_MARKER_ID8[15:0]

0-FFFF

0-FFFF

79

[15:0]

R/W

CTL_TX_VL_MARKER_ID8[31:16]

0-FFFF

0-FFFF

7A

[15:0]

R/W

CTL_TX_VL_MARKER_ID8[47:32]

0-FFFF

0-FFFF

7B

[15:0]

R/W

CTL_TX_VL_MARKER_ID8[63:48]

0-FFFF

0-FFFF

80

[15:0]

R/W

CTL_TX_VL_MARKER_ID9[15:0]

0-FFFF

0-FFFF

81

[15:0]

R/W

CTL_TX_VL_MARKER_ID9[31:16]

0-FFFF

0-FFFF

82

[15:0]

R/W

CTL_TX_VL_MARKER_ID9[47:32]

0-FFFF

0-FFFF

83

[15:0]

R/W

CTL_TX_VL_MARKER_ID9[63:48]

0-FFFF

0-FFFF

88

[15:0]

R/W

CTL_TX_VL_MARKER_ID10[15:0]

0-FFFF

0-FFFF

89

[15:0]

R/W

CTL_TX_VL_MARKER_ID10[31:16]

0-FFFF

0-FFFF

8A

[15:0]

R/W

CTL_TX_VL_MARKER_ID10[47:32]

0-FFFF

0-FFFF

8B

[15:0]

R/W

CTL_TX_VL_MARKER_ID10[63:48]

0-FFFF

0-FFFF

90

[15:0]

R/W

CTL_TX_VL_MARKER_ID11[15:0]

0-FFFF

0-FFFF

91

[15:0]

R/W

CTL_TX_VL_MARKER_ID11[31:16]

0-FFFF

0-FFFF

92

[15:0]

R/W

CTL_TX_VL_MARKER_ID11[47:32]

0-FFFF

0-FFFF

93

[15:0]

R/W

CTL_TX_VL_MARKER_ID11[63:48]

0-FFFF

0-FFFF

98

[15:0]

R/W

CTL_TX_VL_MARKER_ID12[15:0]

0-FFFF

0-FFFF

99

[15:0]

R/W

CTL_TX_VL_MARKER_ID12[31:16]

0-FFFF

0-FFFF

9A

[15:0]

R/W

CTL_TX_VL_MARKER_ID12[47:32]

0-FFFF

0-FFFF

9B

[15:0]

R/W

CTL_TX_VL_MARKER_ID12[63:48]

0-FFFF

0-FFFF

A0

[15:0]

R/W

CTL_TX_VL_MARKER_ID13[15:0]

0-FFFF

0-FFFF

A1

[15:0]

R/W

CTL_TX_VL_MARKER_ID13[31:16]

0-FFFF

0-FFFF

A2

[15:0]

R/W

CTL_TX_VL_MARKER_ID13[47:32]

0-FFFF

0-FFFF

A3

[15:0]

R/W

CTL_TX_VL_MARKER_ID13[63:48]

0-FFFF

0-FFFF

A8

[15:0]

R/W

CTL_TX_VL_MARKER_ID14[15:0]

0-FFFF

0-FFFF

A9

[15:0]

R/W

CTL_TX_VL_MARKER_ID14[31:16]

0-FFFF

0-FFFF

AA

[15:0]

R/W

CTL_TX_VL_MARKER_ID14[47:32]

0-FFFF

0-FFFF

AB

[15:0]

R/W

CTL_TX_VL_MARKER_ID14[63:48]

0-FFFF

0-FFFF

B0

[15:0]

R/W

CTL_TX_VL_MARKER_ID15[15:0]

0-FFFF

0-FFFF

B1

[15:0]

R/W

CTL_TX_VL_MARKER_ID15[31:16]

0-FFFF

0-FFFF

B2

[15:0]

R/W

CTL_TX_VL_MARKER_ID15[47:32]

0-FFFF

0-FFFF

B3

[15:0]

R/W

CTL_TX_VL_MARKER_ID15[63:48]

0-FFFF

0-FFFF

B8

[15:0]

R/W

CTL_TX_VL_MARKER_ID16[15:0]

0-FFFF

0-FFFF

B9

[15:0]

R/W

CTL_TX_VL_MARKER_ID16[31:16]

0-FFFF

0-FFFF

BA

[15:0]

R/W

CTL_TX_VL_MARKER_ID16[47:32]

0-FFFF

0-FFFF

BB

[15:0]

R/W

CTL_TX_VL_MARKER_ID16[63:48]

0-FFFF

0-FFFF

C0

[15:0]

R/W

CTL_TX_VL_MARKER_ID17[15:0]

0-FFFF

0-FFFF

C1

[15:0]

R/W

CTL_TX_VL_MARKER_ID17[31:16]

0-FFFF

0-FFFF

C2

[15:0]

R/W

CTL_TX_VL_MARKER_ID17[47:32]

0-FFFF

0-FFFF

C3

[15:0]

R/W

CTL_TX_VL_MARKER_ID17[63:48]

0-FFFF

0-FFFF

C8

[15:0]

R/W

CTL_TX_VL_MARKER_ID18[15:0]

0-FFFF

0-FFFF

C9

[15:0]

R/W

CTL_TX_VL_MARKER_ID18[31:16]

0-FFFF

0-FFFF

CA

[15:0]

R/W

CTL_TX_VL_MARKER_ID18[47:32]

0-FFFF

0-FFFF

CB

[15:0]

R/W

CTL_TX_VL_MARKER_ID18[63:48]

0-FFFF

0-FFFF

D0

[15:0]

R/W

CTL_TX_VL_MARKER_ID19[15:0]

0-FFFF

0-FFFF

D1

[15:0]

R/W

CTL_TX_VL_MARKER_ID19[31:16]

0-FFFF

0-FFFF

D2

[15:0]

R/W

CTL_TX_VL_MARKER_ID19[47:32]

0-FFFF

0-FFFF

D3

[15:0]

R/W

CTL_TX_VL_MARKER_ID19[63:48]

0-FFFF

0-FFFF

D8

0

R/W

CTL_RX_CHECK_PREAMBLE

FALSE

0

TRUE

1

D9

0

R/W

CTL_RX_IGNORE_FCS

FALSE

0

TRUE

1

DA

0

R/W

CTL_RX_FORWARD_CONTROL

FALSE

0

TRUE

1

DB

0

R/W

CTL_RX_DELETE_FCS

FALSE

0

TRUE

1

E0

0

R/W

CTL_RX_CHECK_ACK

FALSE

0

TRUE

1

E1

0

R/W

CTL_RX_CHECK_SFD

FALSE

0

TRUE

1

E2

0

R/W

CTL_RX_PROCESS_LFI

FALSE

0

TRUE

1

E8

[7:0]

R/W

CTL_RX_MIN_PACKET_LEN[7:0]

40-FF

40-FF

E9

[14:0]

R/W

CTL_RX_MAX_PACKET_LEN[14:0]

40-3FFF

40-3FFF

EA

[15:0]

R/W

CTL_TX_ETHERTYPE_GPP[15:0]

0-FFFF

0-FFFF

EB

[15:0]

R/W

CTL_RX_OPCODE_GPP[15:0]

0-FFFF

0-FFFF

F0

[15:0]

R/W

CTL_RX_OPCODE_MAX_GCP[15:0]

0-FFFF

0-FFFF

F1

[15:0]

R/W

CTL_RX_ETYPE_PPP[15:0]

0-FFFF

0-FFFF

F2

[15:0]

R/W

CTL_RX_ETYPE_GCP[15:0]

0-FFFF

0-FFFF

F3

[15:0]

R/W

CTL_RX_VL_LENGTH_MINUS1[15:0]

0-FFFF

0-FFFF

F8

[15:0]

R/W

CTL_RX_OPCODE_MAX_PCP[15:0]

0-FFFF

0-FFFF

F9

[15:0]

R/W

CTL_RX_OPCODE_MIN_GCP[15:0]

0-FFFF

0-FFFF

FA

[15:0]

R/W

CTL_RX_ETYPE_GPP[15:0]

0-FFFF

0-FFFF

FB

[15:0]

R/W

CTL_RX_OPCODE_MIN_PCP[15:0]

0-FFFF

0-FFFF

100

[15:0]

R/W

CTL_RX_ETYPE_PCP[15:0]

0-FFFF

0-FFFF

101

[15:0]

R/W

CTL_RX_OPCODE_PPP[15:0]

0-FFFF

0-FFFF

108

[15:0]

R/W

CTL_RX_PAUSE_DA_MCAST[15:0]

0-FFFF

0-FFFF

109

[15:0]

R/W

CTL_RX_PAUSE_DA_MCAST[31:16]

0-FFFF

0-FFFF

10A

[15:0]

R/W

CTL_RX_PAUSE_DA_MCAST[47:32]

0-FFFF

0-FFFF

110

[15:0]

R/W

CTL_RX_PAUSE_DA_UCAST[15:0]

0-FFFF

0-FFFF

111

[15:0]

R/W

CTL_RX_PAUSE_DA_UCAST[31:16]

0-FFFF

0-FFFF

112

[15:0]

R/W

CTL_RX_PAUSE_DA_UCAST[47:32]

0-FFFF

0-FFFF

118

[15:0]

R/W

CTL_RX_PAUSE_SA[15:0]

0-FFFF

0-FFFF

119

[15:0]

R/W

CTL_RX_PAUSE_SA[31:16]

0-FFFF

0-FFFF

11A

[15:0]

R/W

CTL_RX_PAUSE_SA[47:32]

0-FFFF

0-FFFF

120

[15:0]

R/W

CTL_RX_VL_MARKER_ID0[15:0]

0-FFFF

0-FFFF

121

[15:0]

R/W

CTL_RX_VL_MARKER_ID0[31:16]

0-FFFF

0-FFFF

122

[15:0]

R/W

CTL_RX_VL_MARKER_ID0[47:32]

0-FFFF

0-FFFF

123

[15:0]

R/W

CTL_RX_VL_MARKER_ID0[63:48]

0-FFFF

0-FFFF

128

[15:0]

R/W

CTL_RX_VL_MARKER_ID1[15:0]

0-FFFF

0-FFFF

129

[15:0]

R/W

CTL_RX_VL_MARKER_ID1[31:16]

0-FFFF

0-FFFF

12A

[15:0]

R/W

CTL_RX_VL_MARKER_ID1[47:32]

0-FFFF

0-FFFF

12B

[15:0]

R/W

CTL_RX_VL_MARKER_ID1[63:48]

0-FFFF

0-FFFF

130

[15:0]

R/W

CTL_RX_VL_MARKER_ID2[15:0]

0-FFFF

0-FFFF

131

[15:0]

R/W

CTL_RX_VL_MARKER_ID2[31:16]

0-FFFF

0-FFFF

132

[15:0]

R/W

CTL_RX_VL_MARKER_ID2[47:32]

0-FFFF

0-FFFF

133

[15:0]

R/W

CTL_RX_VL_MARKER_ID2[63:48]

0-FFFF

0-FFFF

138

[15:0]

R/W

CTL_RX_VL_MARKER_ID3[15:0]

0-FFFF

0-FFFF

139

[15:0]

R/W

CTL_RX_VL_MARKER_ID3[31:16]

0-FFFF

0-FFFF

13A

[15:0]

R/W

CTL_RX_VL_MARKER_ID3[47:32]

0-FFFF

0-FFFF

13B

[15:0]

R/W

CTL_RX_VL_MARKER_ID3[63:48]

0-FFFF

0-FFFF

140

[15:0]

R/W

CTL_RX_VL_MARKER_ID4[15:0]

0-FFFF

0-FFFF

141

[15:0]

R/W

CTL_RX_VL_MARKER_ID4[31:16]

0-FFFF

0-FFFF

142

[15:0]

R/W

CTL_RX_VL_MARKER_ID4[47:32]

0-FFFF

0-FFFF

143

[15:0]

R/W

CTL_RX_VL_MARKER_ID4[63:48]

0-FFFF

0-FFFF

148

[15:0]

R/W

CTL_RX_VL_MARKER_ID5[15:0]

0-FFFF

0-FFFF

149

[15:0]

R/W

CTL_RX_VL_MARKER_ID5[31:16]

0-FFFF

0-FFFF

14A

[15:0]

R/W

CTL_RX_VL_MARKER_ID5[47:32]

0-FFFF

0-FFFF

14B

[15:0]

R/W

CTL_RX_VL_MARKER_ID5[63:48]

0-FFFF

0-FFFF

150

[15:0]

R/W

CTL_RX_VL_MARKER_ID6[15:0]

0-FFFF

0-FFFF

151

[15:0]

R/W

CTL_RX_VL_MARKER_ID6[31:16]

0-FFFF

0-FFFF

152

[15:0]

R/W

CTL_RX_VL_MARKER_ID6[47:32]

0-FFFF

0-FFFF

153

[15:0]

R/W

CTL_RX_VL_MARKER_ID6[63:48]

0-FFFF

0-FFFF

158

[15:0]

R/W

CTL_RX_VL_MARKER_ID7[15:0]

0-FFFF

0-FFFF

159

[15:0]

R/W

CTL_RX_VL_MARKER_ID7[31:16]

0-FFFF

0-FFFF

15A

[15:0]

R/W

CTL_RX_VL_MARKER_ID7[47:32]

0-FFFF

0-FFFF

15B

[15:0]

R/W

CTL_RX_VL_MARKER_ID7[63:48]

0-FFFF

0-FFFF

160

[15:0]

R/W

CTL_RX_VL_MARKER_ID8[15:0]

0-FFFF

0-FFFF

161

[15:0]

R/W

CTL_RX_VL_MARKER_ID8[31:16]

0-FFFF

0-FFFF

162

[15:0]

R/W

CTL_RX_VL_MARKER_ID8[47:32]

0-FFFF

0-FFFF

163

[15:0]

R/W

CTL_RX_VL_MARKER_ID8[63:48]

0-FFFF

0-FFFF

168

[15:0]

R/W

CTL_RX_VL_MARKER_ID9[15:0]

0-FFFF

0-FFFF

169

[15:0]

R/W

CTL_RX_VL_MARKER_ID9[31:16]

0-FFFF

0-FFFF

16A

[15:0]

R/W

CTL_RX_VL_MARKER_ID9[47:32]

0-FFFF

0-FFFF

16B

[15:0]

R/W

CTL_RX_VL_MARKER_ID9[63:48]

0-FFFF

0-FFFF

170

[15:0]

R/W

CTL_RX_VL_MARKER_ID10[15:0]

0-FFFF

0-FFFF

171

[15:0]

R/W

CTL_RX_VL_MARKER_ID10[31:16]

0-FFFF

0-FFFF

172

[15:0]

R/W

CTL_RX_VL_MARKER_ID10[47:32]

0-FFFF

0-FFFF

173

[15:0]

R/W

CTL_RX_VL_MARKER_ID10[63:48]

0-FFFF

0-FFFF

178

[15:0]

R/W

CTL_RX_VL_MARKER_ID11[15:0]

0-FFFF

0-FFFF

179

[15:0]

R/W

CTL_RX_VL_MARKER_ID11[31:16]

0-FFFF

0-FFFF

17A

[15:0]

R/W

CTL_RX_VL_MARKER_ID11[47:32]

0-FFFF

0-FFFF

17B

[15:0]

R/W

CTL_RX_VL_MARKER_ID11[63:48]

0-FFFF

0-FFFF

180

[15:0]

R/W

CTL_RX_VL_MARKER_ID12[15:0]

0-FFFF

0-FFFF

181

[15:0]

R/W

CTL_RX_VL_MARKER_ID12[31:16]

0-FFFF

0-FFFF

182

[15:0]

R/W

CTL_RX_VL_MARKER_ID12[47:32]

0-FFFF

0-FFFF

183

[15:0]

R/W

CTL_RX_VL_MARKER_ID12[63:48]

0-FFFF

0-FFFF

188

[15:0]

R/W

CTL_RX_VL_MARKER_ID13[15:0]

0-FFFF

0-FFFF

189

[15:0]

R/W

CTL_RX_VL_MARKER_ID13[31:16]

0-FFFF

0-FFFF

18A

[15:0]

R/W

CTL_RX_VL_MARKER_ID13[47:32]

0-FFFF

0-FFFF

18B

[15:0]

R/W

CTL_RX_VL_MARKER_ID13[63:48]

0-FFFF

0-FFFF

190

[15:0]

R/W

CTL_RX_VL_MARKER_ID14[15:0]

0-FFFF

0-FFFF

191

[15:0]

R/W

CTL_RX_VL_MARKER_ID14[31:16]

0-FFFF

0-FFFF

192

[15:0]

R/W

CTL_RX_VL_MARKER_ID14[47:32]

0-FFFF

0-FFFF

193

[15:0]

R/W

CTL_RX_VL_MARKER_ID14[63:48]

0-FFFF

0-FFFF

198

[15:0]

R/W

CTL_RX_VL_MARKER_ID15[15:0]

0-FFFF

0-FFFF

199

[15:0]

R/W

CTL_RX_VL_MARKER_ID15[31:16]

0-FFFF

0-FFFF

19A

[15:0]

R/W

CTL_RX_VL_MARKER_ID15[47:32]

0-FFFF

0-FFFF

19B

[15:0]

R/W

CTL_RX_VL_MARKER_ID15[63:48]

0-FFFF

0-FFFF

1A0

[15:0]

R/W

CTL_RX_VL_MARKER_ID16[15:0]

0-FFFF

0-FFFF

1A1

[15:0]

R/W

CTL_RX_VL_MARKER_ID16[31:16]

0-FFFF

0-FFFF

1A2

[15:0]

R/W

CTL_RX_VL_MARKER_ID16[47:32]

0-FFFF

0-FFFF

1A3

[15:0]

R/W

CTL_RX_VL_MARKER_ID16[63:48]

0-FFFF

0-FFFF

1A8

[15:0]

R/W

CTL_RX_VL_MARKER_ID17[15:0]

0-FFFF

0-FFFF

1A9

[15:0]

R/W

CTL_RX_VL_MARKER_ID17[31:16]

0-FFFF

0-FFFF

1AA

[15:0]

R/W

CTL_RX_VL_MARKER_ID17[47:32]

0-FFFF

0-FFFF

1AB

[15:0]

R/W

CTL_RX_VL_MARKER_ID17[63:48]

0-FFFF

0-FFFF

1B0

[15:0]

R/W

CTL_RX_VL_MARKER_ID18[15:0]

0-FFFF

0-FFFF

1B1

[15:0]

R/W

CTL_RX_VL_MARKER_ID18[31:16]

0-FFFF

0-FFFF

1B2

[15:0]

R/W

CTL_RX_VL_MARKER_ID18[47:32]

0-FFFF

0-FFFF

1B3

[15:0]

R/W

CTL_RX_VL_MARKER_ID18[63:48]

0-FFFF

0-FFFF

1B8

[15:0]

R/W

CTL_RX_VL_MARKER_ID19[15:0]

0-FFFF

0-FFFF

1B9

[15:0]

R/W

CTL_RX_VL_MARKER_ID19[31:16]

0-FFFF

0-FFFF

1BA

[15:0]

R/W

CTL_RX_VL_MARKER_ID19[47:32]

0-FFFF

0-FFFF

1BB

[15:0]

R/W

CTL_RX_VL_MARKER_ID19[63:48]

0-FFFF

0-FFFF

1C1

0

R/W

CTL_PTP_TRANSPCLK_MODE

FALSE

0

TRUE

1

1C8

[10:0]

R/W

CTL_TX_PTP_LATENCY_ADJUST[10:0]

0-7FF

0-7FF