This Figure shows the example design hierarchy (GT subcore in core).
This Figure shows the instantiation of various modules and their hierarchy in the example design for GT subcore in core configuration. The cmac_0 module instantiates the 100G Ethernet subsystem and GT along with various helper blocks. Sync registers and pipeline registers are used for the synchronization of data between the 100G Ethernet subsystem and the GT. Clocking helper blocks are used to generate the required clock frequency for the 100G Ethernet subsystem. The cmac_0_pkt_gen_mon module instantiates cmac_0_pkt_gen (packet generator) and cmac_0_pkt_mon (packet monitor).
The cmac_0_pkt_gen_mon and cmac_0 handshake with each other using few signals such as GT locked, RX alignment, and data transfer signals as per the LBUS protocol (more on this will be described in later sections). The cmac_0_pkt_gen module is mainly responsible for the generation of packets. It contains a state machine that monitors the status of the GT and the 100G Ethernet subsystem (that is, GT lock and RX alignment) and sends traffic to the core. Similarly the cmac_0_pkt_mon module is mainly responsible for the reception and checking of packets from the core. It also contains a state machine that monitors the status of the GT and 100G Ethernet subsystem (that is, GT lock and RX alignment) and receives traffic from the core.
Other optional modules instantiated in the example design are as follows:
• cmac_0_trans_debug : This module brings out all the DRP ports of the transceiver module out of the 100G Ethernet subsystem. This module is present in the example design for the following conditions:
° When you select the Runtime Switchable mode in the 100G Ethernet IP AMD Vivado™ Integrated Design Environment (IDE), this module is used to perform the GT DRP writes to change the GT configuration (that is, from CAUI-4 to CAUI-10 / CAUI-10 to CAUI-4). After completion of the DRP write, this module generates the gt _ drp_done signal that is used to reset the GT.
° When you select Enable Additional GT Control/Status and DRP Ports in the CMAC/GT Selection and Configuration Tab of the 100G Ethernet IP Vivado IDE.
• cmac_0_shared_logic_wrapper : When you select Include Shared Logic in example design in the CMAC/GT Selections and Configuration Tab of the 100G Ethernet IP Vivado IDE, this module will be available in the example design. This wrapper contains three modules: cmac_0_clocking_wrapper , cmac_0_reset_wrapper , and cmac_0_common wrapper . The cmac_0_clocking_wrapper has the instantiation of the IBUFDS for the gt_ref_clk , and the cmac_0_reset_wrapper brings out the reset architecture instantiated between the core and the GT. The cmac_0_common_wrapper brings the transceiver common module out of the 100G Ethernet subsystem.
• Pipeline registers : Single-stage pipeline registers are introduced between the 100G Ethernet subsystem and the transceiver when you select Enable Pipeline register in the CMAC/GT Selections and Configuration Tab . This includes a one-stage pipeline register between the 100G Ethernet subsystem macro and the transceiver to ease timing, using the gt_txusrclk2 and gt_rxusrclk2 for the TX and RX paths respectively.
• TX / RX Sync register : The TX Sync register double synchronizes the data between the 100G Ethernet subsystem and the transceiver with respect to the tx_clk . The RX Sync register double synchronizes the data between the transceiver and the 100G Ethernet subsystem with respect to rx_serdes_clk .
• rx_ptp_adjust_top : When you select Enable time stamping in the General Tab , this module is present inside the packet monitor module. This soft logic improves timestamp accuracy and compensate for the lane alignment FIFO fill levels by adding or subtracting the relative fill level of the selected lane. This module has a window averaging block with fixed window size of 32.
• cmac_0_axi4_lite_if_wrapper : When selected with the Include AXI4-Lite Control and Statistics Interface option from the General Tab , this module will be included inside the cmac_0_wrapper . This wrapper contains two modules cmac_0_axi4_lite_reg_map and cmac_0_axi4_lite_slave_2_ipif . The details of these modules are described in AXI4-Lite Interface Implementation .
• cmac_0_axi4_lite_user_if : When selected with the Include AXI4-Lite Control and Statistics option from the General Tab , this module will be present inside the cmac_0_pkt_gen_mon . The details about this module are described in section AXI4-Lite Interface Implementation .
• cmac_0_rs_fec: In CAUI-4 mode of operation, when you select the Include IEEE 802.3bj RS-FEC option from the General Tab , the IEEE 802.3bj RS-FEC soft IP will be instantiated inside the cmac_0_wrapper. This module is meant for forward error correction coding. The RS-FEC IP will be integrated in between CMAC and GT. The details of this module are described in IEEE 802.3bj RS-FEC Integration .
• cmac_0_xbar : In CAUI-4 mode of operation, when you select Include IEEE 802.3bj RS-FEC along with the Include AXI4-Lite Control and Statistics Interface option from the General Tab , the AXI Crossbar soft IP will be instantiated inside the cmac_0_wrapper. The AXI4-Lite interface for both CMAC and RS-FEC will be accessed through the AXI Crossbar IP. The details of this module are described in IEEE 802.3bj RS-FEC Integration .