• Supports CAUI-10, CAUI-4, and runtime switchable between CAUI-4 and CAUI-10 modes
• 512-bit segmented local bus (LBUS) /AXI4-Stream (AXIS) user interface at ~322 MHz
• 32-bit interface to the serial transceiver for CAUI-10 lanes and 80-bit interface to the serial transceiver for CAUI-4 lanes
• Optional fee-based soft 100G RS-FEC for CAUI-4 and runtime switch CAUI-4 modes
• IEEE 1588-2008 [Ref 1] one-step and two-step hardware timestamping at ingress and egress at full 80-bits
• Pause frame processing including priority based flow control per IEEE std 802.3-2012 Annex 31 [Ref 2]
• Dynamic and static deskew support
• Optional fee-based Auto-negotiation and Link Training feature for CAUI-4 mode
• Supports 100GBASE-CR4, 100GBASE-KR4, 100GBASE-SR, 100GBASE-LR4, etc.
See Feature Summary for a list of additional features.
Subsystem Facts Table |
|
---|---|
Subsystem Specifics |
|
Supported Device Family (1) |
AMD Kintex™ UltraScale, AMD Virtex™ UltraScale |
Supported User Interfaces |
Segmented LBUS, AXI4-Stream |
Resources |
|
Provided with Subsystem |
|
Design Files |
Verilog |
Example Design |
Verilog |
Test Bench |
Verilog |
Constraints File |
Xilinx Design Constraints (XDC) |
Simulation Model |
Verilog |
Supported
|
Linux (2) |
Tested Design Flows (3) |
|
Design Entry |
AMD Vivado™ Design Suite |
Simulation |
For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). [Ref 19] |
Synthesis |
AMD Vivado synthesis |
Support |
|
Release Notes and Known Issues |
Master Answer Record: 58696 |
All Vivado IP Change Logs |
|
Notes: 1. For a complete list of supported devices, see the AMD Vivado IP catalog. 2. Create a Service Request for 100G Ethernet Control Plane driver. 3. For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). [Ref 19] |