IEEE 802.3bj RS-FEC Integration - 2.6 English

UltraScale Devices Integrated 100G Ethernet Subsystem Product Guide (PG165)

Document ID
PG165
Release Date
2023-06-15
Version
2.6 English

If you want to include IEEE 802.3bj RS-FEC soft IP (for error correction) in between CMAC and GT, you must tick mark the Include IEEE 802.3bj RS-FEC check box in the General tab. This option is active for CAUI-4 mode of operation only.

Figure 5-18: RS-FEC Integration between CMAC and GT

X-Ref Target - Figure 5-18

rs_fec_integration.jpg

This feature enables the IEEE 802.3bj RS-FEC soft IP component instantiated in between the CMAC core and the GT. The TX SerDes lines from the CMAC core will be input to the RS-FEC soft IP for forward error correction encoding. The output from the RS-FEC module then fed to GT. Similarly, the RX SerDes lines from the GT will be fed to RS-FEC module for error correction decoding then to CMAC core. Refer to the 100G IEEE 802.3bj Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG197) [Ref 14] .

The AXI Crossbar soft IP along with the AXI4-Lite User Interface modules are instantiated when you select Include AXI4-Lite Control and Statistics Interface with RS-FEC enable. The AXI Crossbar IP is configured with 1-master and 2-slave interfaces. Both CMAC and RS-FEC modules control and status ports registers can be accessed with AXI4-Lite interface through AXI Crossbar. Refer to the AXI Interconnect LogiCORE IP Product Guide (PG059) [Ref 15] for AXI Crossbar soft IP functionality.

The base address locations for CMAC control and status registers and RS-FEC control and status registers in the AXI Crossbar soft IP are configured as shown:

0x0000_0000 to 0x0000_0FFF: Address locations for CMAC

0x0000_1000 to 0x0000_1FFF: Address locations for RS-FEC

For IEEE 802.3bj RS-FEC IP, the address location for the input rs_fec_ctrl_in is 0x0000_1000.