The module cmac_0_pkt_gen is responsible for the generation of LBUS packets. Typically the packet generator waits for the GT to achieve lock and for the core RX to get aligned. After this has occurred, the packet generator sends a predefined number of packets. A Finite State Machine (FSM) is used to generate the LBUS packets. A functional description of each state follows:
• STATE_TX_IDLE : By default the controller is in the STATE_TX_IDLE state. When reset_done becomes High, it moves to the STATE_GT_LOCKED state.
• STATE_GT_LOCKED : This state sets ctl_tx_send_rfi =1, tx_core_busy_led =1 and gt_lock_led =1. It then moves to the STATE_WAIT_RX_ALIGNED state.
• STATE_WAIT_RX_ALIGNED : This state waits for the 100G Ethernet subsystems to indicate stat_rx_aligned =1, which means that the 100G Ethernet IP RX core is locked. After that, it moves to the STATE_PKT_TRANSFER_INIT state.
• STATE_PKT_TRANSFER_INIT : This state sets rx_aligned_led =1 and tx_core_busy_led =1. It then initializes all signals to start LBUS packet generation and moves to the STATE_LBUS_TX_ENABLE state.
• STATE_LBUS_TX_ENABLE : This state checks for the number of packets to be generated and sends LBUS packets of a predefined size. After sending all the packets, the FSM moves to the STATE_LBUS_TX_DONE state. During transmission of the packets, if tx_rdyout =0, tc_ovfout =1 or tx_unfout =1, the FSM controller moves to the STATE_LBUS_TX_HALT state.
• STATE_LBUS_TX_HALT : In this state, the controller generates the tx_fail_reg flag if tc_ovfout or tx_unfout is High. Then the FSM moves to the STATE_LBUS_TX_DONE state. If tx_rdyout becomes High, the FSM moves to the STATE_LBUS_TX_ENABLE state to proceed with packet generation.
• STATE_LBUS_TX_DONE : This state resets all signals related to packet generation and sets tx_done_led =1. If the 1588 "1-step" or "Both" option with FCS insertion is enabled, FSM moves to the STATE_PTP_PKT_INIT state; otherwise it checks if TX_FLOW_CONTROL is enabled. If enabled, the FSM moves to the STATE_TX_PAUSE_INIT state. If TX_FLOW_CONTROL is now enabled, the FSM moves to the STATE_WAIT_FOR_RESTART state.
• STATE_WAIT_FOR_RESTART : In this state, all the packet generator parameters reset to the default values and reset tx_busy_led =0. The FSM moves to STATE_PKT_TRANSFER_INIT at tx_restart_rising_edge .
• STATE_PTP_PKT_INIT : Reset all the signals used for LBUS transactions. Move to the STATE_PTP_PKT_READ state wait until the initialization counter is done and set the ptp_pkt_transfer flag to one. After sending three 1588 PTP packets (Ethernet, IPV4 and IPV6), FSM moves to the STATE_TX_PAUSE_INIT state if the TX_FLOW_CONTROL is enabled; otherwise FSM moves to STATE_WAIT_FOR_RESTART state.
• STATE_PTP_PKT_READ : In case of IPV4 or IPV6, increment the tx_ptp_pkt_index and move to the STATE_PTP_PKT_TRANSFER state.
• STATE_TX_PTP_PKT_TRANSFER : Read the data from the ptp_pkt_gen module after sending the complete ptp packet, move to the STATE_PTP_PKT_INIT state.
• STATE_TX_PAUSE_INIT : Set the ctl_tx_pause_enable = 9’h100 and ctl_tx_pause_req[8] = 1 and wait for the stat_tx_pause signal to become High and the FSM moves to the STATE_TX_PPP_INIT state.
• STATE_TX_PPP_INIT : In this state, the controller sets ctl_tx_pause_enable = 9'h0ff and ctl_tx_pause_req[7:0] one bit at a time in decrementing order (bit 7 to bit 0). It then waits for stat_tx_pause_valid[0] to become High and moves to the STATE_TX_PAUSE_DONE state.
• STATE_TX_PAUSE_DONE : In this state, all the pause signals are reset. The controller then moves to the STATE_WAIT_FOR_RESTART state.
Notes:
• If any time stat_rx_aligned = 0, the FSM moves to STATE_TX_IDLE.
• In the simplex TX mode of operation because RX alignment information will not be available, the state machine waits for you to input simplex_mode_rx_aligned . After you assert this input to High, packet transmission starts.
•
If you select the
Disable FCS Insertion
option in the
General Tab
, the CMAC core will not insert the CRC value for the data packets. So a
CRC_Mapping_LUT
module will be instantiated inside the
cmac_0_pkt_gen
module that contains the pre-calculated CRC values for the current LBUS predefined data packet of the packet size 522 bytes. These CRC values will be appended at the end of each LBUS packet.|
Therefore, if you are changing the packet size, you must change the CRC values for this new module as appropriate for the new packet and/or packet size.
If the 1588 Transparent Clock
1-step
or
Both
option is selected and if FCS insertion is disabled in Vivado IDE, the 1588 Transparent Clock testing will not be performed in the example design because of the unpredictable PTP frame CRC values as the core will modify the packet.
• If you select the 1-step or Both option in the General Tab , then the ptp_packet_gen module will be instantiated inside the cmac_0_packet_gen module. This module contains three 1588 PTP packets (Ethernet, IPV4 and IPV6) with or without the CRC values based on the Disable FCS Insertion or Enable FCS Insertion option in the General Tab .
The state transition that occurs during this process is shown in This Figure .
