The 100G Ethernet subsystem is designed to operate with the performance characteristics of the CMAC primitive it instantiates.
See the Virtex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics (DS893) [Ref 3] for the maximum frequencies allowed on the 100G Ethernet subsystem specified by speed grade.
IMPORTANT: A free-running clock input, init_clk , is required for the transceiver portion of the 100G Ethernet subsystem. See the UltraScale FPGAs Transceiver Wizards (PG182) [Ref 4] for more information on the gtwiz_reset_clk_freerun_in input port.