Table: Integrated CMAC Block for the 100 Gb/s Ethernet Solution defines the integrated CMAC block for the 100 Gb/s Ethernet solution.
|
Protocol |
Lane Width |
Line Rate |
SerDes |
SerDes Width |
|---|---|---|---|---|
|
CAUI-10 |
x10 |
10.3125 Gb/s |
GTH GTY |
32b |
|
CAUI-4 |
x4 |
25.78125 Gb/s (2) |
GTY (1) |
80b |
|
Runtime Switchable CAUI-4/CAUI-10 |
CAUI-10: x10 CAUI-4: x4 |
CAUI-10: 10.3125 Gb/s CAUI-4: 25.78125 Gb/s |
GTY (1) |
CAUI-10: 32b CAUI-4: 80b |
|
1. CAUI-4 and switchable CAUI-10/CAUI-4 require GTY transceivers that are available only in AMD Virtex™ UltraScale™ devices. 2. The line rate of 25.78125 Gb/s is available on select devices, AMD Virtex UltraScale devices in typical speed grades. |
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The core instantiates the CMAC block along with the necessary GTH or GTY transceivers. The core provides an example of how the two blocks are connected together, along with the reset and clocking for those blocks.
The integrated block is designed to IEEE std 802.3-2012 [Ref 2] .
This Figure illustrates the following interfaces to the integrated CMAC block.
• Serial transceiver interface
• User-side transmit and receive LBUS or AXIS interface
• Pause processing
• IEEE 1588-2008 [Ref 1] timestamping interface
• Status/Control interface
• Dynamic reconfiguration port (DRP) interface used for configuration
