References - 2.6 English

UltraScale Devices Integrated 100G Ethernet Subsystem Product Guide (PG165)

Document ID
PG165
Release Date
2023-06-15
Version
2.6 English

These documents provide supplemental material useful with this product guide:

1. IEEE 1588-2008 ( standards.ieee.org/findstds/standard/1588-2008.html )

2. IEEE std 802.3-2012 ( standards.ieee.org/findstds/standard/802.3-2012.html )

3. Virtex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics ( DS893 )

4. UltraScale FPGAs Transceiver Wizards ( PG182 )

5. 10G/25G High Speed Ethernet Subsystem Product Guide ( PG210 )

6. UltraScale Architecture Clocking Resource User Guide ( UG572 )

7. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator ( UG994 )

8. Vivado Design Suite User Guide: Designing with IP ( UG896 )

9. Vivado Design Suite User Guide: Getting Started ( UG910 )

10. Vivado Design Suite User Guide: Logic Simulation ( UG900 )

11. Vivado Design Suite User Guide: Using Constraints ( UG903 )

12. UltraScale FPGAs GTH Transceivers User Guide ( UG576 )

13. UltraScale FPGAs GTY Transceivers User Guide ( UG578 )

14. 100G IEEE 802.3bj Reed-Solomon Forward Error Correction (PG197) — Access in lounge

15. AXI Interconnect LogiCORE IP Product Guide ( PG059 )

16. Vivado Design Suite User Guide: Programming and Debugging ( UG908 )

17. ISE to Vivado Design Suite Migration Guide ( UG911 )

18. Vivado Design Suite User Guide: Implementation ( UG904 )

19. Vivado Design Suite User Guide: Release Notes, Installation, and Licensing ( UG973 )