|
Date |
Version |
Revision |
|---|---|---|
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06/15/2023 |
2.6 |
• Updated Table: LBUS Interface – TX Path Control/Status Signals . • Added a note in User Side AXI4-Stream Interface section. • Updated Table: CORE XCI Top-Level Port List . |
|
11/22/2022 |
2.6 |
• Updated Supported Simulators . • Added Riviera-PRO Simulator . |
|
11/26/2021 |
2.6 |
Editorial updates only, No technical content updates. |
|
02/04/2021 |
2.6 |
Chapter 5: Example Design • Updated Table: RESET_REG . Updated Validation Steps for Auto-Negotiation and Link Training with AXI4-Lite Interface . |
|
06/24/2020 |
2.6 |
Chapter 2: Product Specification • Updated Table: IEEE 1588 Interface – TX Path . Chapter 4: Design Flow Steps • Updated This Figure , This Figure , and This Figure . Chapter 5: Example Design • Updated Table: CORE XCI Top-Level Port List . • Added RS-FEC Enabled Configuration Simulation . Appendix A: Auto-Negotiation and Link Training • Added Validation Steps for Auto-Negotiation and Link Training with AXI4-Lite Interface . Appendix C: Debugging |
|
05/22/2019 |
2.5 |
Chapter 2: Product Specification • Added AXI4-Stream interface to bullet. • Added AXI4-Stream description in Typical Operation . Chapter 3: Designing with the Core • Added User Side AXI4-Stream Interface section. Chapter 4: Design Flow Steps • Updated figures. • Added AXIS and Include Statistics Counters and Statistics Resource Type parameters in Table: General Tab . Chapter 5: Example Design • Added AXI4-Stream TX and RX in Table: CORE XCI Top-Level Port List . • Added table note in Table: Status and Statistics Register Map . • Added Bits[15:11] in Table: CONFIGURATION_AN_ABILITY . • Updated Bits[13, 6] Type in Table: STAT_AN_STATUS_REG . • Updated Bits[19:11] in Table: STAT_AN_ABILITY_REG . • Updated Bits[31:22] in Table: STAT_AN_LINK_CTL_REG_1 . • Added new register Table: STAT_AN_LINK_CTL_REG_2 . Appendix A: Auto Negotiation and Link Training Updated Bits[5:0] description in Table: Status Report Field Bit Definitions . |
|
12/05/2018 |
2.4 |
Chapter 3: Designing with the Core • Updated This Figure to This Figure and This Figure . Chapter 4: Design Flow Steps • Updated figures. • Removed 161.13 from GT RefClk and User Interface parameter in Table: General Tab . Chapter 5: Example Design • Updated gt_rxusrclk2 and added user_reg0 in Table: CORE XCI Top-Level Port List . • Added USER_REG0 in Table: Configuration Register Map . • Added Table: USER_REG0 . |
|
04/04/2018 |
2.3 |
• Updated descriptions for STAT_RX_PCSL_NUMBER_0[4:0] to STAT_RX_PCSL_NUMBER_19[4:0] throughout. Chapter 5: Example Design • Added the gt_txpippmen, gt_txpippmsel, and stat_reg_compare_out ports. • Defined the .h Header File. • Updated register names: ° STAT_RX_PCSL_DEMUXED to STAT_RX_PCSL_DEMUXED_REG ° STAT_AN_STATUS to STAT_AN_STATUS_REG ° STAT_AN_LINK_CTL to STAT_AN_LINK_CTL_REG ° STAT_AN_ABILITY to STAT_AN_ABILITY_REG • Updated 0x023C-0x0254 and 0x027C-0x02AF as reserved addresses. • Added 0x0258 to 0x0278 address, and removed 0x0758 to 0x0778. |
|
10/04/2017 |
2.3 |
Chapter 5: Example Design • Updated the port s_axi_pm_tick to pm_tick. • Updated the port description for rx_serdes_clk. • Added the port send_continuous_pkts. • Updated connections in Figure 5-12. • Updated the “Configuration Register Map” table and the “Status and Statistices Register Map” table with new registers & addresses. • Updated the Core Bring Up Sequence section. Appendix A: Auto-Negotiation and Link Training • Updated the port ctl_an_cl91_ability to ctl_an_cl91_fec_ability. |
|
06/07/2017 |
2.2 |
• Updated document title: removed "Block for", and added subsystem. • Changed signal names stat_rx_vl_* to stat_rx_pcsl_* throughout. Chapter 3: Designing with the Core • Added Frame-by-Frame Timestamping Operation section. Chapter 5: Example Design • Added the gt_powergoodout and gt_ref_clk_out signals. • Updated the Configuration Register Map table. Appendix C: Debugging • Added the PCS Lane Mapping debug step (Hardware Debug). |
|
04/05/2017 |
2.1 |
• Added a new appendix for the auto-negotiation and link training features. |
|
11/30/2016 |
2.0 |
Chapter 2: Product Specification • Updated the TX_RDYOUT port description. • Updated bus values for STAT_RX_BAD_FCS, STAT_RX_STOMPED_FCS, STAT_RX_UNDERSIZE, STAT_RX_FRAGMENT, and STAT_RX_BAD_CODE. Chapter 5: Example Design • Minor editorial updates. • Changed the axi_gt_loopback port name to ctl_gt_loopback. • Updated the drp_addr port description. • Updated default values for bit 0 and bit 1 in the STAT_RX_STATUS_REG table. • Updated default values for bit 19:0 and bit 31:20 in the STAT_RX_BLOCK_LOCK_REG table. • Updated default values for bit 19:0 and bit 31:20 in the STAT_RX_LANE_SYNC_REG table. |
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10/05/2016 |
2.0 |
Facts Table • Added early access Linux software driver support. Chapter 2: Product Specification • Updated the Clock Domain for CTL_RX_SYSTEMTIMERIN[80-1:0]. • Updated the Default Value for CTL_RX_OPCODE_PPP[15:0] and CTL_TX_OPCODE_PPP[15:0]. Chapter 3: Designing with the Core • Added further details about Synchronous Mode and Asynchronous Mode in the Resets section. Chapter 4: Design Flow Steps • Changed GT Selections and Configuration tab to CMAC / GT Selections and Configuration tab throughout. Chapter 5: Example Design • Added new Example Design Hierarchy (GT Subcore in Example Design) section, and diagram. • Added the tx_clk, gtwiz_userdata_tx_in, gtwiz_userdata_rx_out, txdata_in, txctrl0_in, txctrl1_in, rxdata_out, rxctrl0_out, rxctrl1_out, gt_txinhibit, axi_gt_reset_all, and axi_gt_loopback signals. • Updated the Configuration Register Map table. • Added the GT_LOOPBACK_REF table. • Added Simulation Speed Up section. Appendix B: Debugging • Added GTRXRESET requirement information to the Clocking and Resets section under Hardware Debug. |
|
06/08/2016 |
1.10 |
Chapter 3: Designing with the Core • Updated the RX PCS lane de-multiplexing details in Figure 3-5. • Updated the corrected timestamp calculation and explanation in Receive Timestamp Function. Chapter 4: Design Flow Steps • Updated all the tab figures. • Updated the last parameter label in the GT Selections and Configuration tab to Enable Additional GT Control/Status and DPR Ports. All references also updated throughout the guide. Chapter 5: Example Design • Removed cmac_0_common_wrapper module. • Added the cmac_0_shared_logic_wrapper module. • Updated the description for init_clk in Table 5-2. |
|
04/06/2016 |
1.9 |
• Changed Runtime Selectable mode to Runtime Switchable mode. • Added the new parameters: GT DRP/Init Clock, RX Insertion Loss at Nyquist (dB), RX Equalization Mode, PLL Type • Removed the Channel Topology parameter. • Added s_axi_pm_tick to the User I/O Port List in the Example Design chapter. • Added gt_rxusrclk2 to the CORE XCI Top Level Port List in Example Design chapter. |
|
11/18/2015 |
1.8 |
Added licensing and ordering information for the soft IEEE 802.3 RS-FEC. |
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09/30/2015 |
1.7 |
Chapter 2, Product Specification • Added the Domain column to all of the tables in the Port Descriptions section Chapter 3: Designing with the Core • Updated Figure 3-1 through Figure 3-4 and the descriptions of these figures. • Updated the description of a pause packet in the TX Pause Generation section Chapter 4: Design Flow Steps • Updated all the tab figures and the tables describing these tabs. • Removed the text in the User Parameters section. Chapter 5: Example Design • Updated Figure 5-1 and added descriptions of the new blocks, cmac_0_rs_fec and cmac_0_axi4_lite_user_if. • Added new I/O ports to Table 5-1. Updated other ports. • Added the new Core XCI ports table to Chapter 5 • Updates throughout based on the new and changed fields in Vivado IDE. • Added a note about CAUI-4 mode to the AXI4-Lite Interface Implementation • Added new Figure 5-10, GT Ref Clock Connectivity when Channels Operating above 16.375 Gb/s. • Updated Figure s 5-1, 5-7, 5-8, 5-11, 5-12, 5-13, 5-14, 5-15, 5-16, and 5-17. • Updated Tables 5-1, 5-2, 5-5 and all of the tables in the Register Description. section (Table 5-7 through Table 5-43). • Added the new IEEE 802.3bj RS-FEC Integration section. Appendix A: Added Changes from v1.6 to v1.7 section. |
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06/24/2015 |
1.6 |
Chapter 3: Designing with the Core • Updated Figure 3-1 through Figure 3-4. Chapter 4: Design Flow Steps • Updated screen captures: Figures 4-1 through 4-3. Chapter 5: Example Design • Updated Figure 5-1, Figure 5-7, Figure 5-11, Figure 5-17, Figure 5-18, Figure 5-19, Figure 5-20, Figure 5-21, Figure 5-22, Figure 5-23 • Updated switch_caui_mode description in Table 5-1. • Replaced tx_fail_led with caui_mode_led in Table 5-1. • Updated descriptions for STATE_GT_LOCKED, STATE_LBUS_TX_DONE, STATE_WAIT_FOR_RESTART, STATE_LBUS_RX_DONE, STATE_PKT_TRANSFER_INIT. • Removed STATE_SWITCH_CMAC_MODE • Changed Figure 5-23 title to “Board Validation for Runtime Selectable configuration - Passing Scenario.” |
|
04/01/2015 |
1.5 |
Chapter 4: Design Flow Steps • Updated Figures 4-1, 4-2, and 4-3. • Updated Table 4-3: GT Selections and Configuration • Added Enable AXI4-Lite Interface parameter to Table 4-1:General Tab Chapter 5: Example Design • Updated lbus_tx_rx_restart_in description in Table 5-1. • Added two new ports to Table 5-1: simplex_mode_rx_aligned and switch_caui_mode. • Added cmac_0_axi4_lite_if_wrapper, cmac_0_axi4_lite_user_if, STATE_PTP_PKT_INIT, STATE_PTP_PKT_READ, STATE_TX_PTP_PKT_TRANSFER, STATE_RX_PTP_ENABLE, and STATE_RX_PTP_DONE • Updated all of the figures. • Added Simplex TX Mode Simulation, Simplex RX Mode Simulation sections. • Added extensive Notes. • Added new section, AXI4-Lite Interface. |
|
01/22/2015 |
1.4 |
• Updated the Vivado® IDE screen captures. • Updated the clocking and reset diagram. • Corrected the maximum packet length. |
|
10/01/2014 |
1.3 |
• Updated information on the segmented LBUS in Chapter 3, “Designing with the Core.” • Removed Appendix C, Segmented LBUS Protocol. |
|
06/04/2014 |
1.2 |
• Updated core to v1.2. • Added example design clocking information. |
|
04/02/2014 |
1.1 |
• Added DRP blocks to Figure 2-1. • Added transceiver selection rules. • Updated General table • Added resources and performance characteristics. • Updated screen displays in Chapter 4, Figure 5-1, and Figure 5-5. • Provided description of other optional modules instantiated in the example design. • Updated Control/Pause Packet Processing table. • Updated GT Selections and Configurations table. • Added new constraints information. • Added DRP information. • Added Shared Logic Implementation and Runtime Selectable sections. |
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12/18/2013 |
1.0 |
Initial Xilinx release. |