Signal List to Add to ILA for Debug - 2.6 English

UltraScale Devices Integrated 100G Ethernet Subsystem Product Guide (PG165)

Document ID
PG165
Release Date
2023-06-15
Version
2.6 English

sys_reset

an_reset

ctl_an_*

ctl_lt_*

stat_an_start_tx_disable

stat_an_rxcdrhold

stat_an_lp_autoneg_able

stat_an_lp_ability_valid

stat_an_start_an_good_check

stat_lt_frame_lock

stat_lt_signal_detect

stat_lt_link_training

stat_lt_link_training_fail

stat_rx_block_lock

stat_rx_synced (only available on multi-lane cores)

stat_rx_aligned (only available on mult-lane cores)

stat_rx_valid_ctrl_code (only available on 10G/25G core)

stat_rx_status

stat_rx_bad_code

stat_rx_hi_ber

If you are using a line rate that supports Clause 74 Fire code FEC, the signal list is as follows:

stat_fec_inc_cant_correct_count

stat_fec_lock_error

stat_fec_rx_lock

stat_fec_inc_correct_count

ctl_an_fec_10g_request

ctl_fec_rx_enable

ctl_fec_tx_enable

stat_an_fec_enable

stat_an_lp_fec_10g_ability

stat_an_lp_fec_10g_request

If you are using a line rate that supports RS-FEC, the signal list is as follows:

ctl_tx_rsfec_enable

ctl_rx_rsfec_enable

stat_rx_rsfec_am_lock

stat_an_rs_fec_enable