Transceiver Selection Rules - 2.6 English

UltraScale Devices Integrated 100G Ethernet Subsystem Product Guide (PG165)

Document ID
PG165
Release Date
2023-06-15
Version
2.6 English

The design must meet the following rules when connecting the 100G Ethernet subsystem to the transceivers.

If implementing CAUI-10:

CAUI-10 GTs have to be contiguous

CAUI-10 must include two or four GTs from the quad in the same horizontal Clock Region (CR) as the 100G Ethernet IP

CAUI-10 must be implemented within an Super Logic Region (SLR)

If implementing CAUI-4:

CAUI-4 GTs have to be contiguous

CAUI-4 must use GTs from the same horizontal CR or two above or below

CAUI-4 all GTs must come from the same GT quad

CAUI-4 is only supported in Lanes 1-4

CAUI-4 must be implemented within an SLR

If implementing Runtime Switchable CAUI-10/CAUI-4, follow the preceding rules for both CAUI-10 and CAUI-4 rules.

IMPORTANT: For Runtime Switchable mode, if the GT group is selected as two GTs from bottom quad, four GTs from middle and four GTs from upper quad, then when it switches from CAUI10 to CAUI4, the upper GT quad is used for CAUI4.

Note that the 100G Ethernet subsystem is optimized to use GTY transceiver locations. Therefore GTH transceiver locations relative to the CMAC block span a significant distance. Timing closure can be affected.

RECOMMENDED: For transceiver selections outside of these rules, contact AMD support or your local FAE.

See the UltraScale Architecture Clocking Resource User Guide (UG572) [Ref 6] for more information on clock region.