This Figure
through
This Figure
show timing diagram waveforms for the AXI4-Lite interface.
•
Valid Write transactions (
This Figure
)
•
Invalid Write transactions (
This Figure
)
•
Valid Read transactions (
This Figure
)
•
Invalid Read transactions (
This Figure
)
.
Figure 5-14:
AXI4-Lite User Side Write Transaction
|
X-Ref Target - Figure 5-14
|
Figure 5-15:
AXI4-Lite User Side Write Transaction with Invalid Write Address
|
X-Ref Target - Figure 5-15
|
Figure 5-16:
AXI4-Lite User Side Read Transaction
|
X-Ref Target - Figure 5-16
|
Figure 5-17:
AXI4-Lite User Side Read Transaction with Invalid Read Address
|
X-Ref Target - Figure 5-17
|
