Channel Bonding and Clock Correction Sequence - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

Page 6 of the Wizard (This Figure) allow you to define the channel bonding sequence(s). Table: Channel Bonding and Clock Correction Sequences describes the sequence definition settings and Table: Clock Correction Setup describes the clock setup settings.

Figure 4-15:      Channel Bonding and Clock Correction Sequence—Page 6

X-Ref Target - Figure 4-15

pg168_viv_cb_cc_sequence.png
Table 4-32:      Channel Bonding and Clock Correction Sequences

Option

Description

Byte (Symbol)

Set each symbol to match the pattern the protocol requires. The XAUI sequence length is 8 bits. 01111100 is used for channel bonding. 00011100 is used for clock correction. The other symbols are disabled because the sequence length is set to 1.

K Character

This option is available when 8B/10B decoding is selected. When checked, as is the case for XAUI, the symbol is an 8B/10B K character.

Inverted Disparity

Some protocols with 8B/10B decoding use symbols with deliberately inverted disparity. This option should be checked when such symbols are expected in the sequence.

Don’t Care

Multiple-byte sequences can have wild card symbols by checking this option. Unused bytes in the sequence automatically have this option set.

Notes:

1.Options not used by the XAUI example are shaded.