Clocking - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID

PG168

Release Date

2022-05-19

Version

3.6 English

The Clocking tab of the Wizard (This Figure) allows you to select the clocking for the octal and the enabled channels within an octal. You can verify all the settings and selections made on this tab graphically with the image shown below the settings.

1.Select the source for TXOUTCLK0 and TXOUTCLK1 of the octal as per Table: TX/RXOUTCLKs of the Octal.

2.Select the source for RXOUTCLK<0-3> of the octal as per Table: TX/RXOUTCLKs of the Octal.

Table 4-2: TX/RXOUTCLKs of the Octal
Options	Description
TXOUTCLK<0-1>	These can be sourced from the TXOUTCLKs from any of the individual channels (only channels enabled on page 1). This selection applies identically for all the octals enabled on page 1.
RXOUTCLK<0-3>	These can be sourced from the RXOUTCLKs from any of the individual channels that were selected on page 1). This selection applies identically for all the octals on page 1.

Figure 4-6: Octal and Channel Clocking—GTZ Page 2
X-Ref Target - Figure 4-6

3.Select the source for the user clocks TX/RXUSRCLK<0-7> (Table: TX/RXUSRCLKs of the Octal). The USRCLK numbering shown here in the Vivado IDE is relative to OCTAL0. These USRCLKs are mapped internally (by the Wizard) to octal1 as follows:

Table 4-3: TX/RXUSRCLKs of the Octal
Options	Description
TXUSRCLK<0-7>	The available sources will be the TXOUTCLKs of the active octals selected in page 1.
RXUSRCLK<0-7>	The available sources will be the RXOUTCLKs of the active octals selected in page 1.

•TX/RXUSRCLK0 – TX/RXUSRCLK4

•TX/RXUSRCLK1 – TX/RXUSRCLK5

•TX/RXUSRCLK2 – TX/RXUSRCLK6

•TX/RXUSRCLK3 – TX/RXUSRCLK7

•TX/RXUSRCLK4 – TX/RXUSRCLK0

•TX/RXUSRCLK5 – TX/RXUSRCLK1

•TX/RXUSRCLK6 – TX/RXUSRCLK2

•TX/RXUSRCLK7 – TX/RXUSRCLK3

4.Channel clocking: First select the channel number for which you wish to configure the clocking.

5.In the TX/RXOUTCLK source for the channel selected above, the only supported sources are TX/RX FIFO CLKs.

6.In the TX/RXUSRCLK LANE sel, select the USRCLK that you wish to source for this channel. For channels of octal1, the USRCLK selection made here will be automatically mapped by the wizard as shown in step 3.

7.Select the source for the DRPCLK.

Table 4-4: Channel Clocking
Options	Description
TXOUTCLK source	Select the TXOUTCLK source for each channel. Only the TX FIFO CLK is supported. Selecting the TX FIFO CLK selects TXOUTCLKPMA_DIV4 (see the 7 Series FPGAs GTZ Transceivers User Guide (UG478) [Ref 12] for more information).
RXOUTCLK source	Select the RXOUTCLK source for each channel. Only the RX FIFO CLK is supported. Selecting the RX FIFO CLK selects RXOUTCLKPMA_DIV4 (see the 7 Series FPGAs GTZ Transceivers User Guide (UG478) [Ref 12] for more information).
TXUSRCLK lane sel	Select one among the available eight TX user clocks.
RXUSRCLK lane sel	Select one among the available eight RX user clocks.