This section includes information about using Xilinx tools to customize and generate the core in the Vivado Design Suite.
If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 3] for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.
The 7 series FPGA transceiver core can be customized to suit a wide variety of requirements using the IP catalog. This chapter details the available customization parameters and how these parameters are specified within the IP catalog interface.
The 7 series FPGA transceiver core can be found in FPGA Features and Design > IO Interface in the Vivado IP Catalog.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using these steps:
1.Select the IP from the IP catalog.
2.Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu .
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9] and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 10].
Note: Figures in this chapter are illustrations of the Vivado IDE. This layout might vary from the current version.
This Figure shows the 7 series FPGA transceiver Wizard Customize IP dialog boxes with customizing information.
