Debugging Using Embedded BERT - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

In 7\ series FPGA transceivers, there is an in-built PRBS function generator (pattern generator) on the transmit PCS, and PRBS function checker (pattern checker) on the receiver PCS that can be used for the Bit Error Rate Test (BERT). PRBS 7-bit, PRBS 15-bit, PRBS 23-bit, and PRBS 31-bit are available in the 7\ series transceivers. These can be controlled using the TXPRBSSEL[2:0] port as:

000: No PRBS pattern generation

001: Enables 27-1 PRBS checker

010: Enables 215-1 PRBS checker

011: Enables 223-1 PRBS checker

100: Enables 231-1 PRBS checker

101: PCIe technology compliance pattern generation

110: Generation of square wave with 2 UI period

111: Generation of square wave with 16/20/32/40 UI period (depending on data width)

Errors in the bitstream can be forced based on the value driven on TXPRBSFORCEERR.

0: No errors are forced in the PRBS transmitter

1: Errors are forced in the PRBS transmitter. The output data pattern contains errors. When TXPRBSSEL is set to 000, this port does not affect TXDATA.

The RXPRBSCNTRESET port can be used to reset the error counter in the transceiver and RXPRBSERR can be monitored to identify when an error occurred. The RX_PRBS_ERR_CNT attribute can be read out through the DRP to validate the PRBS error counter value.