You can change 7\ series FPGA transceiver ports and attributes. The DRP interface logic allows the run-time software to monitor and change any attribute of the transceivers and the corresponding CPLL/QPLL. Readable and writable registers are also included that are connected to the various ports of the transceiver. All are accessible at run-time using the Vivado serial I/O analyzer to debug DRP- and port-related issues.