The example design generated by the CAUI4 protocol template of the Wizard also includes a dynamic phase deskew logic within it to ensure the lane-to-lane skew is minimized. This logic is found in the gt_usrclk_source.v module generated in the example_design folder. This logic, with the help of the MMCM, adjusts the phase of the RXFIFO read clock to get the maximum margin on the right side without losing too much on the left margin.
•You need to set the M, D, and O values of the MMCM to get the required VCO frequency and resolution. The resolution is 1/56 FVCO.
•The MMCM uses the dynamic phase variation feature. An FSM controls the phase shift of USRCLK using the phase shift interface.
•Shifting starts whenever RXRESETDONE is asserted from all channels. The Low-to-High transition of the RXRESETDONE signal triggers the adjustment again.
•You should assert the RXFIBRESET once after the MMCM is locked. This ensures that the RX FIFO is reset after the phase adjustments are done on the read clock.
•Each channel has different left and right margins, but it is guaranteed to be above (3.1 + 1.5) when operated at 25.8 Gb/s.
•Whenever the link goes down and is later re-established using a new training sequence, it is possible to get a different write clock phase. This training sequence is always followed by an RXFIFO reset to bring the FIFO to a normal operating condition. In that case, RXRESETDONE to the deskew logic toggles and re-initiates the phase adjustment.