Page 3 of the Wizard (This Figure) allows you to select encoding and 8B/10B optional ports. Tables 4-13 through 4-20 list the available options.
Figure 4-12: Encoding and Optional Ports—Page 3
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X-Ref Target - Figure 4-12
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Table 4-13: TX Settings
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Options
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Description
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External Data Width
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16
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Sets the transmitter application interface data width to two 8-bit bytes.
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20
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The transmitter application interface datapath width is set to 20 bits.
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32
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Sets the transmitter application interface data width to two 8-bit bytes.
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40
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Sets the transmitter application interface data width to 40 bits.
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64
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Sets the transmitter application interface datapath width to eight 8-bit bytes (64 bits).
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80
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Sets the transmitter application interface data width to 80 bits.
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Encoding
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8B/10B
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Data stream is passed to an internal 8B/10B encoder prior to transmission.
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64B/66B_with_Ext_Seq_Ctr
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Data stream is passed through the 64B/66B gearbox and scrambler. Sequence counter for the gearbox is implemented in the example design.
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64B/66B_with_Int_Seq_Ctr
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GTX transceivers only: Data stream is passed through the 64B/66B gearbox and scrambler. Sequence counter for the gearbox is implemented within the transceiver.
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64B/67B_with_Ext_Seq_Ctr
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Data stream is passed through the 64B/67B gearbox and scrambler. Sequence counter for the gearbox is implemented in the example design.
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64B/67B_with_Int_Seq_Ctr
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GTX transceivers only: Data stream is passed through the 64B/67B gearbox and scrambler. Sequence counter for the gearbox is implemented within the transceiver.
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Internal Data Width
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16
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Selects the internal data width as 16.
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20
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Selects the internal data width as 20.
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32
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Selects the internal data width as 32.
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40
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Selects the internal data width as 40.
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Notes:
1.Options not used by the XAUI example are shaded.
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Table 4-14: RX Settings
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Options
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Description
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External Data Width
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16
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Sets the receiver application interface data width to two 8-bit bytes.
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20
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Sets the receiver application interface data width to 20 bits.
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32
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Sets the receiver application interface datapath width to four 8-bit bytes (32 bits).
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40
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Sets the receiver application interface data width to 40 bits.
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64
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Sets the receiver application interface datapath width to eight 8-bit bytes (64 bits).
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80
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Sets the receiver application interface data width to 80 bits.
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Decoding
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8B/10B
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Data stream is passed to an internal 8B/10B decoder.
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64B/66B
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Data stream is passed through the 64B/66B gearbox and de-scrambler.
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64B/67B
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Data stream is passed through the 64B/67B gearbox and de-scrambler.
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Internal Data Width
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16
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Selects the internal data width as 16.
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20
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Selects the internal data width as 20.
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32
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Selects the internal data width as 32.
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40
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Selects the internal data width as 40.
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Notes:
1.Options not used by the XAUI example are shaded.
2.RX settings should be the same as TX settings.
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Table 4-15: DRP
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Option
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Description
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Use DRP
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Select this option to have the dynamic reconfiguration port signals of the CHANNEL block available to the application
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The TX PCS/PMA Phase Alignment setting controls whether the TX buffer is enabled or bypassed. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] for details on this setting. The RX PCS/PMA alignment setting controls whether the RX phase alignment circuit is enabled.
Table: 8B/10B Optional Ports shows the optional ports for 8B/10B.
Table 4-16: 8B/10B Optional Ports
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Option
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Description
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TX
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TXBYPASS8B10B
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2-bit wide port disables 8B/10B encoder on a per-byte basis. High-order bit affects high-order byte of datapath.
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TXCHARDISPMODE
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2-bit wide ports control disparity of outgoing 8B/10B data. High-order bit affects high-order byte of datapath.
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TXCHARDISPVAL
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RX
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RXCHARISCOMMA
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2-bit wide port flags valid 8B/10B comma characters as they are encountered. High-order bit corresponds to high-order byte of datapath.
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RXCHARISK
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2-bit wide port flags valid 8B/10B K characters as they are encountered. High-order bit corresponds to high-order byte of datapath.
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Notes:
1.Options not used by the XAUI example are shaded.
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Table: TX and RX Buffer Bypass Options shows the TX and RX buffer bypass options.
Table 4-17: TX and RX Buffer Bypass Options
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Option
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Description
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TX
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Enable TX Buffer
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If the Enable TX Buffer checkbox is checked, the TX buffer in the transceiver is enabled. This buffer can be bypassed for low, deterministic latency.
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TX
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TX Buffer Bypass Mode
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This option is only if the TX buffer is bypassed. It is mandatory to use the manual mode. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] for details.
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RX
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Enable RX Buffer
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If the Enable RX Buffer checkbox is checked, the RX elastic buffer in the transceiver is enabled. This buffer can be bypassed for low, deterministic latency.
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RX
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RX Buffer Bypass Mode
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This option is visible only if the RX buffer is bypassed. Auto mode is the recommended setting. To use manual mode, see the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7].
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Table: TXUSRCLK and RXUSRCLK Source details the TXUSRCLK and RXUSRCLK source signal options.
Table 4-18: TXUSRCLK and RXUSRCLK Source
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Option
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Description
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TX
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TXOUTCLK
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TXUSRCLK is driven by TXOUTCLK.
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RX
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TXOUTCLK
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RXUSRCLK is driven by TXOUTCLK. This option is not available if the RX buffer is bypassed. For RX buffer bypass mode, RXOUTCLK is used to source RXUSRCLK.
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Table: TXOUTCLK and RXOUTCLK Source details the TXOUTCLK and RXOUTCLK source signal options.
Table 4-19: TXOUTCLK and RXOUTCLK Source
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Option
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Description
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TX
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Use TXPLLREFCLK
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If the check box Use TXPLLREFCLK is checked, TXOUTCLK(1) is generated from the input reference clock; otherwise, the Wizard selects the appropriate source for TXOUTCLK.
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RX
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Use RXPLLREFCLK
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If the check box Use RXPLLREFCLK is checked, RXOUTCLK(1) is generated from the input reference clock; otherwise, the Wizard selects the appropriate source for RXOUTCLK.
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Notes:
1.See 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] for more information on TXOUTCLK and RXOUTCLK control.
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Table: Optional Ports shows the optional ports available for latency and clocking.
Table 4-20: Optional Ports
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Option
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Description
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TXPCSRESET
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Active-High reset signal for the transmitter PCS logic.
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TXBUFSTATUS
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2-bit signal monitors the status of the TX elastic buffer. This option is not available when the TX buffer is bypassed.
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TXRATE
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Transmit rate change port.
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RXPCSRESET
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Active-High reset signal for the receiver PCS logic.
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RXBUFSTATUS
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Indicates condition of the RX elastic buffer. Option is not available when the RX buffer is bypassed.
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RXBUFRESET
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Active-High reset signal for the RX elastic buffer logic. This option is not available when the RX buffer is bypassed.
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RXRATE
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Receive rate change port.
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QPLLPD
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Visible only when GTX or GTH transceiver is selected. Powerdown port for QPLL.
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CPLLPD
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Visible only when GTX or GTH transceiver is selected. Powerdown port for CPLL.
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PLL0PD
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Visible only when GTP transceiver is selected. Powerdown port for PLL0.
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PLL1PD
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Visible only when GTP transceiver is selected. Powerdown port for PLL1.
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TXSYSCLKSEL
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Selects the reference clock source to drive the TX datapath.
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RXSYSCLKSEL
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Selects the reference clock source to drive the RX datapath.
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TXPMARESET
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Active-High reset signal for the transmitter PMA logic.
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RXPMARESET
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Active-High reset signal for the receiver PMA logic.
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TX8B10BEN
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TX8B10BEN is set High to enable the 8B/10B encoder.
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RXCDRHOLD
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Holds the CDR control loop frozen.
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SIGVALIDCLK
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Visible for GTH or GTP transceiver. Clock for OOB circuit.
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CLKRSVD
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Visible for GTX transceiver. Clock for OOB circuit.
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TXPIPPMEN
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Enables the TX phase interpolator PPM control block.
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TXPIPPMOVRDEN
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Enables direct control of TXPI.
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TXPIPPMPD
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Power downs the TX interpolator PPM control block.
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TXPIPPMSTEPSIZE
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Specifies the amount to increment or decrement PI code.
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Notes:
1.Options not used by the XAUI example are shaded.
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