Example Design Hierarchy - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

The hierarchy for the design used in this example is:

EXAMPLE_TB

|___CAUI4_WRAPPER_EXDES

   |___CAUI4_INIT

   |   |___CAUI4_WRAPPER

   |   |    |___CAUI4_WRAPPER_OCTAL0 (1 per octal)

   |   |    |___GTWIZARD_V3_4_BEACHFRONT (1 per octal)

   |   |

   |   |___CAUI4_WRAPPER_CTLE_TUNING (1 per octal)

   |   |___CAUI4_WRAPPER_RX_STARTUP_FSM (1 per channel)

   |

   |___CAUI4_WRAPPER_GT_FRAME_GEN_TOP (1 per channel)

   |   |___CAUI4_WRAPPER_GT_FRAME_GEN

   |   |___CAUI4_WRAPPER_SCRAMBLER (5 per channel)

   |

   |___CAUI4_WRAPPER_GT_FRAME_CHECK_TOP (1 per channel)

   |   |___CAUI4_WRAPPER_GT_FRAME_CHECK (5 per channel)

   |   |___CAUI4_WRAPPER_DESCRAMBLER (5 per channel)

   |   |___CAUI4_WRAPPER_BLOCK_SYNC_SM (5 per channel)

   |

   |___CAUI4_WRAPPER_GT_USRCLK_SOURCE (contains MMCM and dynamic phase deskew)