False Paths - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

The system clock and user clock are not related to one another. No phase relationship exists between these two clocks. The two clock domains need to be set as false paths. The set_false_path XDC command is used to constrain the false paths.