Integrated Bit Error Ratio Tester (IBERT) core for the 7\ series FPGA transceivers is designed for evaluating and monitoring the transceivers, and is supported by the Vivado design tools available in the IP catalog under Debug & Verification. Because communication logic is included in IBERT, it allows the design to be run-time accessible through JTAG, through which transceiver debug can be done on hardware.
IBERT design has a pattern generator and a pattern checker that sends a generated pattern through the transmitter and accepts data through the receiver and checks it against internally generated patterns. The following condition qualifies the link:
•Link Up: When the checker receives five consecutive cycles of data with no errors, the LINK signal is asserted in IBERT.
•Link Down: If the LINK signal is asserted and the checker receives five consecutive cycles with data errors, the LINK signal is deasserted.
If you see the Link Down issue in IBERT, use the Vivado Design Suite debug feature IBERT design to validate the serial transceiver link. The debug feature IBERT design also allows you to optimize serial transceiver link parameters during run-time.