As discussed in Design Flow Steps, customize the core per the requirements, generate the core, and follow these steps:
1.In the Project Manager window of the Vivado IP catalog, right-click the core and select Open IP Example Design. A new Vivado IDE opens with the core example design files.
2.Open <component_name>_exdes.v[hd] and change EXAMPLE_USE_CHIPSCOPE from 0 to 1 to enable debugging using the Vivado Design Suite debug feature cores.
3.Open <component_name>_0.v[hd] and change EXAMPLE_SIMULATION value from 1 to 0 as shown below:
.EXAMPLE_SIMULATION (0),
4.Open <component_name>_exdes.xdc and make sure that the GTREFCLK_PAN_N_IN and GTREFCLK_PAD_P_IN location is proper.
Example:
set_property LOC J7 [get_ports Q2_CLK0_GTREFCLK_PAD_N_IN ]
set_property LOC J8 [get_ports Q2_CLK0_GTREFCLK_PAD_P_IN ]
5.Make sure that the GTXE2_CHANNEL location is set properly in <component_name>_exdes.xdc.
Example:
set_property LOC GTXE2_CHANNEL_X0Y8 [get_cells gtwiz_eou_test2_support_i/gtwiz_eou_test2_init_i/inst/gtwiz_eou_test2_i/
gt0_gtwiz_eou_test2_i/gtxe2_i]
6.Click Run Synthesis and after synthesis is completed, click Open Synthesized Design. The tool runs for some time to synthesize and open the synthesized netlist.
7.When the synthesized design is opened, enter write_debug_probes <ltx_file_name> in the Tcl console and press Enter. This command creates <ltx_file_name>.ltx under the <component_name>_example folder.
8.Click Generate Bitstream which generates routed.bit in the <component_name>_example folder. If you see any errors while generating the BIT file, click Open Implemented Design. If implementation is already done, the operation opens the implemented design. If not, the tool runs for some time to implement and open the implemented design.
9.When the implemented design is opened, enter the following comments in the Tcl console to generate the routed.bit bitstream:
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]; set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit -force
10.Ensure that the board setup is arranged according to these steps:
a.TXP from board 1 should be connected to RXP in board 2, and TXN from board 1 should be connected to RXN in board 2.
b.Similarly, TXP from board 2 should be connected to RXP in board 1, and TXN from board 2 should be connected to RXN in board 1.
c.The reference clock to each KC705 board should be fed from a different source, as shown in This Figure.
11.When the bit file is generated, click File > Open Hardware Session, as shown in This Figure.
12.A new window appears, as shown in This Figure. Click Open a new hardware target.
13.The Open New Hardware Target window opens, as shown in This Figure. Click Next.
14.Enter the server name to which the KC705 board is connected in Vivado CSE Server Name, as shown in This Figure, and click Next. The Vivado IDE automatically connects to the server and detects all boards connected to the server.
15.The Select Hardware Target window opens with all targeted boards connected to the server, as shown in This Figure. Select the board that you want to program and click Next to set the targeted hardware JTAG properties.
16.Set Hardware Target Properties allows you to choose any JTAG clock speed from the drop-down menu to program the targeted hardware. Choose the desired clock frequency and click Next.
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X-Ref Target - Figure C-12 
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17.Review the targeted hardware summary and click Finish, as shown in This Figure.
18.Browse to and specify the bitstream file (<routed>.bit) location in the programming file, and probe file (<probfile.ltx>) location in the Probes file as shown in This Figure.
19.Right-click the device and select Program Device as shown in This Figure and This Figure. Make sure the bit file location is correct, and click OK.
20.When programing is finished on board 1, right-click the programmed device and select Close Target, as shown in This Figure.
21.To program board 2, select the second device, right-click the device, and select Open Target, as shown in This Figure.
22.Repeat step 18 and step 19 to program board 2 with the same programming file and probe file that was downloaded on the first KC705 board. After programing is complete, right-click the device and select Refresh Device, as shown in This Figure. You should be able to see all nets that are added to the ILA cores.
23.Right-click the device again and select Run Trigger. You will be able to see all the ILA cores debug signals in the waveform, as shown in This Figure.
Notes:
•Make sure that the signals have the values shown in the RX ILA waveform window (This Figure):
°gt0_rxdata_i[63:0] = some random 64-bit value
°gt0_error_count = 00
°gt0_frame_check = 1
°gt0_rxreset_done = 1
°track_data_out_i = 1
•Make sure that the signal has the following value as shown in the TX ILA waveform window (This Figure):
°gt0_txresetdone_i = 1
24.Similarly, you can monitor the GTX transceiver transaction for the first KC705 board by repeating step 21 and step 22 to validate board 1.