General Design Guidelines - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

Line rate selection should be compatible with the device and speed grade chosen in the project settings.

The Start Up finite state machines (FSMs) given in the example design are mainly to demonstrate a proper reset initialization sequence. You need to fine-tune the counter settings in the FSMs per the design requirements.

The design needs to be constrained per the constraints generated by the Wizard. You need to add additional constraints based on the board requirements.

Every version of the Wizard is associated with a specific silicon version for GTX, GTH, GTP, and GTZ transceivers. Follow AR 46048 to ensure the appropriate version is chosen.