Generation of TX/RXUSRCLK and TX/RXUSRCLK2 - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)
Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

The Wizard generates the TXUSRCLK/TXUSRCLK2 as follows:

•TXUSRCLK and TXUSRCLK2 are always generated using the TXOUTCLK, which is the output of the transceiver.

•As given in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7], the source for the TXOUTCLK can be the reference clock or the PMA clock.

Table 3-2:      TXOUTCLK Configuration Setting

TX Buffer Bypassed

Source for TXOUTCLK

Yes

Set to Reference Clock. You cannot change the selection in the Vivado IDE.

No

You can select Reference Clock or PMA Clock on Page 2 of the Vivado IDE.

The Wizard generates the RXUSRCLK/RXUSRCLK2 as follows:

•RXUSRCLK and RXUSRCLK2 can be generated using TXOUTCLK or RXOUTCLK, which are the outputs of the transceiver.

•As given in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG 476) [Ref 7], the source for the RXOUTCLK can be the reference clock or the recovered clock.

Table 3-3:      RXOUTCLK Configuration Setting

RX Buffer Bypassed

Source for RXUSRCLK

Source for RXOUTCLK

Yes

Set to RXOUTCLK. You cannot change the selection in the Vivado IDE.

Set to Recovered Clock. You cannot change the selection in the Vivado IDE.

No

You can select TXOUTCLK or RXOUTCLK on Page 2 of the Vivado IDE.

You can select Reference Clock or Recovered Clock on Page 2 of the Vivado IDE.