Hardware Debug - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

The 7 series FPGAs Transceivers Wizard core has an option to use the Vivado Design Suite debug feature in the example design. Debugging and ensuring proper operation of the transceiver is extremely important in any protocol that uses the 7 series FPGAs Transceivers Wizard core. The 7 series FPGAs Transceivers Wizard core example design has a VIO core instantiated and connected with important status and control signals for validating the design in board.

To assist with debugging, these VIO cores are provided with the 7 series FPGAs Transceivers Wizard wrapper, which is enabled by setting EXAMPLE_USE_CHIPSCOPE to 1 in the <component_name>exdes.v[hd] file. This Figure shows the steps involved in debugging transceiver related issues.

Figure C-3:      Transceiver Debug Flow Chart

X-Ref Target - Figure C-3

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Attribute updates with respect to the device silicon version transceiver attributes must match with the silicon version of the device being used in the board. Apply all the applicable workarounds and Answer Records given for the relevant silicon version.

The EXAMPLE_SIMULATION parameter must be set to 0 in the top-level 7 series FPGAs Transceivers Wizard wrapper to enable hardware debugging.

GT REFCLK Check

A low-jitter differential clock must be provided to the transceiver reference clock. Connecting the onboard differential clock to the transceiver will narrow down the issue to the external clock generation and/or external clock cables connected to the transceiver.

GT PLL Lock Check

The transceiver locks into the incoming GT REFCLK and asserts the PLLLOCK signal. This signal is available as the PLLLOCK_OUT signal in the transceiver core example design. Make sure that the GT PLL attributes are set correctly and that the transceiver generates TXOUTCLK and RXOUTCLK with the expected frequency for the given line rate and datapath width options.

GT Reset

In the 7 series FPGAs Transceivers Wizard core, RX resets can operate in two different modes: sequential mode and single mode. The TX reset can operate only in sequential mode. Reset modes have no impact on CPLL/QPLL resets. The TXRESETDONE and RXRESETDONE signals are asserted at the end of the transceiver initialization. In general, RXRESETDONE assertion takes a longer time compared to TXRESETDONE assertion. Make sure the GT_RESET signal pulse width duration matches with the respective transceiver guidelines. The TXRESETDONE and RXRESETDONE signals are available in the 7 series FPGAs Transceivers Wizard core example design to monitor.

GT Initialization Sequence

The 7 series FPGA transceiver must be initialized after device power-up and configuration before it can be used. See AR 43482 for details on the initialization requirements. The TX and RX datapaths must be initialized only after the associated PLL is locked. The transceiver TX and RX initialization comprises two steps:

a.Initializing the associated PLL driving TX/RX

b.Initializing the TX and RX datapaths (PMA + PCS)

Loopback Configuration Testing

Loopback modes are specialized configurations of the transceiver datapath where the traffic stream is folded back to the source. The LOOPBACK port in the 7 series FPGAs Transceivers Wizard core example design will transmit a specific traffic pattern and then compare to check for errors and control the loopback modes. Loopback test modes fall into two broad categories:

°Near-end loopback modes loop transmit data back in the transceiver closest to the traffic generator. Near-end loopback modes are:

-Near-end PCS loopback

-Near-end PMA loopback

°Far-end loopback modes loop received data back in the transceiver at the far end of the link. Far-end loopback modes are:

-Far-end PMA loopback

-Far-end PCS loopback

Loopback testing can be used either during development or in deployed equipment for fault isolation. The traffic patterns used can be either application traffic patterns or specialized pseudo-random bit sequences. The loopback operations are controlled by the LOOPBACK[2:0] ports:

°000: Normal operation

°001: Near-end PCS loopback

°010: Near-end PMA loopback

°011: Reserved

°100: Far-end PMA loopback

°101: Reserved

°110: Far-end PCS loopback

°111: Reserved

Four loopback modes are available. See the respective transceiver user guides for guidelines and more information. This Figure illustrates a loopback test configuration with four different loopback modes.

Figure C-4:      Loopback Test Modes

X-Ref Target - Figure C-4

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