•Dynamic phase deskew is necessary to reduce the lane-to-lane deskew for multi-lane protocols like CAUI4 operating at greater than 25G per line. You are required to reuse the code as shown in the <component_name>_gt_usrclk_source.v module to achieve the same.
•Even though RXFIBRESET is listed as an optional port, this is always brought out to the top level of the example design to enable users to control the RX FIFO reset for operations like CTLE tuning and dynamic phase deskew logic.