•The 7 series FPGAs Transceivers Wizard core wrapper can be generated with asymmetrical data width from the Wizard but simulation support for asymmetrical data width is not supported for the core.
•Generation of the 7 series FPGAs Transceivers Wizard core with different encoding and decoding styles for RX and TX is removed from the Wizard.
•The simulation for Artix-7 device designs and some Virtex-7 device GTH designs takes more time to complete because the silicon work-around modules take more time to finish.
The 20-UI Square Wave figure in 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] shows the process of TX phase and delay alignment. This sequence is not followed by the exdes generated by the 7 series FPGAs Transceivers Wizard in simulation. Instead, the S_TXPHINIT line asserts at the same time as the M_TXPHINIT signal. Also contrary to the figure, the M_TXPHINITDONE signal only asserts when all of the other TXPHINITDONE signals have asserted. The slave TXPHINITDONE signals all assert at different times. There is a disconnect between the figure in 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) and the actual operation of the Wizard example design. The 7 series FPGAs Transceivers Wizard example design simulation is correct.