Line Rate, Transceiver Selection, and Clocking - 3.6 English

Line Rate

Set to the desired target line rate in Gb/s. Can be independent of the receive line rate. The XAUI example uses 3.125 Gb/s.

Reference Clock

Select from the list the optimal reference clock frequency to be provided by the application. The XAUI example uses 156.25 MHz.

TX off

Selecting this option disables the TX path of the transceiver. The transceiver will act as a receiver only.

The XAUI example design requires both TX and RX functionality.

Note:   Options not used by the XAUI example are shaded.

Line Rate

Set to the desired target line rate in Gb/s. The XAUI example uses 3.125 Gb/s.

Reference Clock

Select from the list the optimal reference clock frequency to be provided by the application. The XAUI example uses 156.25 MHz.

RX off

Selecting this option disables the RX path of the transceiver. The transceiver will act as a transmitter only. The XAUI example design requires both TX and RX functionality.

Note:   Options not used by the XAUI example are shaded.

Use Common DRP

Select this option to have the dynamic reconfiguration port signals of the COMMON block available to the application.

Advanced Clocking Option

Use this check box to bring out all possible reference clock ports to the generated wrapper. Used for dynamic clock switching.

Vivado Design Suite Debug Feature

Use this check box to bring out the ILA and VIO cores in IP for hardware debugging and control. For more details on debugging using the ILA and VIO cores in hardware, refer to 7\ Series GT Wizard Hardware Validation on the KC705 Evaluation Board.

GT

Select the individual transceivers by location to be used in the target design. The XAUI example requires four transceivers.

TX Clock Source

Determines the source for the reference clock signal provided to each selected transceiver (see Table: Reference Clock Source Options). Two differential clock signal input pin pairs, labeled REFCLK0 and REFCLK1 are provided for every four transceivers. The groups are labeled Q0 through Q4 starting at the bottom of the transceiver column. Each transceiver has access to the local signal group and one or two adjacent groups depending upon the transceiver position. The XAUI example uses the REFCLK0 signal from the group local to the four selected transceivers (REFCLK0 Q0 option).

RX Clock Source

QPLL

GTX and GTH transceivers: Use the Quad PLL when all four transceivers of the Quad are used to save power. Quad PLL is shared across four transceivers of a Quad.

CPLL

GTX and GTH transceivers: Use the Channel PLL based on the line rate supported by the selected transceiver.

PLL0

GTP transceivers only: PLL0 is shared across four transceivers of a Quad.

PLL1

GTP transceivers only: PLL1 is shared across four transceivers of a Quad.

REFCLK0/1 Q0

Reference clock local to transceivers Y0-Y3.

REFCLK0/1 Q1

Reference clock local to transceivers Y4-Y7.

REFCLK0/1 Q2

Reference clock local to transceivers Y8-Y11.

REFCLK0/1 Q3

Reference clock local to transceivers Y12-Y15.

REFCLK0/1 Q4

Reference clock local to transceivers Y16-Y19.

REFCLK0/1 Q5

Reference clock local to transceivers Y20-Y23.

REFCLK0/1 Q6

Reference clock local to transceivers Y24-Y27.

REFCLK0/1 Q7

Reference clock local to transceivers Y28-Y31.

REFCLK0/1 Q8

Reference clock local to transceivers Y32-Y35.