Generate the 7 series FPGAs Transceivers Wizard v3.4 from the Vivado tools 2014.3 IP catalog as described in Design Flow Steps.
RECOMMENDED: Since the introduction of CSL and moving the common module from the multi-transceiver level, legacy 7 series FPGAs Transceivers Wizard IP users have to make some changes in their design depending on the wrapper file they are using. These changes are listed below.
•Using individual transceiver wrapper files:
The user has to update the new ports added for transceiver debug in their design. For details on the new ports, refer to Table: Transceiver Control and Status Interface.
•Using multi-transceiver wrapper files:
The user has to generate the wizard with the "shared logic in core" option, then manually instantiate the generated common file (<component_name>_common.v[hd]) in the design and update the new transceiver debug ports along with these ports:
For GTX/GTH transceivers: qplloutclk, qplloutrefclk, qplllock
For GTP transceivers: pll0[1]outclk, pll0[1]outrefclk, pll0[1]lock
c) Using the Init wrapper file:
The user has to generate the wizard with the "shared logic in core" option, then manually instantiate the generated common file (<component_name>_common.v[hd]) in the design and update the new transceiver debug ports along with these ports:
For GTX/GTH transceivers: qplloutclk, qplloutrefclk, qplllock
For GTP transceivers: pll0[1]outclk, pll0[1]outrefclk, pll0[1]lock