Optional Ports - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

Page 4 of the Wizard (This Figure) allows you to select the optional ports to bring out to the example top and multi-transceiver wrapper.

Figure 4-8:      Optional Ports—GTZ Page 4

X-Ref Target - Figure 4-8

pg169_viv_optional_ports.png

 

Table 4-6:      Optional Ports for GTZ Transceivers

Options

Description

TXFIBRESET

Brings out the TXFIBRESET ports to the example design from which you can control the RESET of the FIB portion of the GTZ transceiver.

RXFIBRESET

Brings out the RXFIBRESET ports to the example design from which you can control the RESET of the FIB portion of the GTZ transceiver.

TXFIFOSTATUS

Brings out the TXFIFOSTATUS port to the example design allowing you to learn the FIFO status.

RXFIFOSTATUS

Brings out the RXFIFOSTATUS port to the example design allowing you to learn the FIFO status.

TXRATESEL

Brings the TXRATESEL ports out onto the example top level. These ports are used to control the TX PLL divider ratios.

RXRATESEL

Brings the RXRATESEL ports out onto the example top level. These ports are used to control the RX PLL divider ratios.

TXPOLARITY

Brings out the TXPOLARITY port to the example design.

RXPOLARITY

Brings out the RXPOLARITY port to the example design.

TXEN

Brings out the TXEN port to the example design.

RXEN

Brings out the RXEN port to the example design.

TXOUTPUTEN

Brings out the TXOUTPUTEN port to the example design.

TXATTNCTRL

Brings out the TXATTNCTRL port to the example design.

TXEQPOSTCTRL

Brings out the TXEQPOSTCTRL port to the example design.

TXEQPRECTRL

Brings out the TXEQPRECTRL port to the example design.

TXSLEWCTRL

Brings out the TXSLEWCTRL port to the example design.

RXBITSLIP

Brings out the RXBITSLIP port onto the example design. This port can be used to slip data in raw mode.

RXSIGNALOK

Brings out the RXSIGNALOK port onto the example design.

CORECNTL

Brings out the CORECNTL ports onto the example design.

REFSEL

Brings out the REFSEL ports onto the example design.

PLLRECALEN

Brings out the PLLRECALEN ports onto the example design.

RXPRBS

Brings out all the RXPRBS related ports onto the example design.

TXPRBS

Brings out all the TXPRBS related ports onto the example design.

LOOPBACK

Brings out all the LOOPBACK control ports onto the example design.