For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9].
This section provides detailed information about the files and the directory structure generated by the Xilinx Vivado design tools.
The customized 7 series FPGA transceiver core is delivered as a set of HDL source modules in the language selected in the IP catalog project with supporting files. These files are arranged in a predetermined directory structure under the project directory name provided to the IP catalog when the project is created as shown in this section mentioned below.
<component name>_example
Contains Vivado project and log files
<component name>_example.src\sources_1
IP core and example design files
constrs_1\imports\example_design
Example design constraint file
sim_1\imports\simulation
Simulation test bench file
source_1/ip/<component name>
IP Core source files directory
<component name>
IP core Verilog/VHDL source files
<component name>\example_design\
Verilog/VHDL files for example design
<component name>
Vivado Design Suite debug feature files
<imports\<component name>
<component name>\example_design\
Verilog/VHDL files for example design
<example_design>\<support>
Shared logic resource files