Output Generation - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9].

This section provides detailed information about the files and the directory structure generated by the Xilinx Vivado design tools.

The customized 7 series FPGA transceiver core is delivered as a set of HDL source modules in the language selected in the IP catalog project with supporting files. These files are arranged in a predetermined directory structure under the project directory name provided to the IP catalog when the project is created as shown in this section mentioned below.

inset_000007.jpg<component name>_example

       Contains Vivado project and log files

        inset_1.jpg<component name>_example.src\sources_1

               IP core and example design files

              inset_2.jpgconstrs_1\imports\example_design

                    Example design constraint file

              inset_3.jpgsim_1\imports\simulation

                   Simulation test bench file

              inset_4.jpgsource_1/ip/<component name>

                    IP Core source files directory

 inset_5.jpg<component name>

         IP core Verilog/VHDL source files

   inset_6.jpg<component name>\example_design\

         Verilog/VHDL files for example design

   inset_7.jpg<component name>

         Vivado Design Suite debug feature files

            inset_8.jpg<imports\<component name>

                     inset_9.jpg<component name>\example_design\

                                   Verilog/VHDL files for example design

                     inset_10.jpg<example_design>\<support>

                                   Shared logic resource files