The major change to the core is the introduction of a new Core Support Level (CSL) which can be controlled by an option in the GUI to use shared logic at the core level or in the generated example design as shown in This Figure.
When the 7 series FPGAs Transceivers Wizard core is generated with the include Shared Logic in core option selected, the wrapper and RTL files for the core support level are available in the directory /<project_name>/<component_name>.srcs/sources_1/
ip/<component_name>/.
When the 7 series FPGAs Transceivers Wizard core is generated with the include Shared Logic in example design option selected, the wrapper and RTL file for the core support level is available in the directory /<project_name>/<component_name>_example/
<component_name>_example.srcs/sources_1/imports/example_design/
support.
Also, the core support level wrapper file includes instantiations of <component_name>_GT_USRCLK_SOURCE.v[hd], <component_name>_common.v[hd], <component_name>_common_reset.v[hd], and <component_name>_init.v[hd]. For GTX/GTH transceivers, QPLL can be shared between four different transceivers from the same Quad. A separate wrapper file (<component_name>_common.v[hd]) for GTXE2_COMMON/GTHE2_COMMON primitives gets generated and can be used for generating a QPLL reference clock for transceivers of the same Quad. For GTP transceivers, PLL0/PLL1 can be used across the four Quads, thus a separate wrapper file (<component_name>_common.v[hd]) for GTPE2_COMMON primitives gets generated.