Page 5 of the Wizard (This Figure) allows you to configure the receiver for PCI Express and Serial ATA (SATA) features. In addition, configuration options for the RX out-of-band (OOB) signal, pseudo-random bitstream sequence (PRBS) detector, and channel bonding and clock correction settings are provided.
Table: Receiver Serial ATA Options details the receiver SATA configuration options.
Table: PCI Express and SATA Parameters details the receiver PCI Express configuration options.
Option |
Description |
|
---|---|---|
Transition Time |
To P2 |
Integer value between 0 and 65,535. Sets a counter to determine the transition time to the P2 power state for PCI Express. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] for details on determining the time value for each count. The XAUI example does not require this feature and uses the default setting of 100. |
From P2 |
Integer value between 0 and 65,535. Sets a counter to determine the transition time from the P2 power state for PCI Express. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] for details on determining the time value for each count. The XAUI example does not require this feature and uses the default setting of 60. |
|
To/From non-P2 |
Integer value between 0 and 65,535. Sets a counter to determine the transition time to or from power states other than P2 for PCI Express. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] for details on determining the time value for each count. The XAUI example does not require this feature and uses the default setting of 25. |
|
Optional Ports |
LOOPBACK |
3-bit signal to enable the various data loopback modes for testing. |
RXSTATUS |
3-bit receiver status signal. The encoding of this signal is dependent on the setting of RXSTATUS encoding format. |
|
RXVALID |
Active-High, PCI Express RX OOB/beacon signal. Indicates symbol lock and valid data on RXDATA and RXCHARISK[3:0]. |
|
COMINITDET |
Active-High initialization detection signal. |
|
COMSASDET |
Active-High detection signal for SATA. |
|
COMWAKEDET |
Active-High wake up detection signal. |
|
TXCOMINIT |
Transmit initialization port. |
|
TXCOMSAS |
OOB signal. |
|
TXCOMWAKE |
OOB signal. |
|
COMFINISH |
Completion of OOB. |
|
TXDETECTRX |
PIPE interface for PCI Express specification-compliant control signal. Activates the PCI Express receiver detection feature. Function depends on the state of TXPOWERDOWN, RXPOWERDOWN, TXELECIDLE, TXCHARDISPMODE, and TXCHARDISPVAL. This port is not available if RXSTATUS encoding format is set to SATA. |
|
TXELECIDLE |
Drives the transmitter to an electrical idle state (no differential voltage). In PCI Express mode this option is used for electrical idle modes. Function depends on the state of TXPOWERDOWN, RXPOWERDOWN, TXELECIDLE, TXCHARDISPMODE, and TXCHARDISPVAL. |
|
PHYSTATUS |
PCI Express receive detect support signal. Indicates completion of several PHY functions. |
|
TXPOWERDOWN |
Powerdown port for the transmitter. |
|
RXPOWERDOWN |
Powerdown port for the receiver. |
|
Notes: 1.Options not used by the XAUI example are shaded. |
Table: OOB Signal Detection shows the OOB signal detection options.
Option |
Description |
---|---|
Use RX OOB Signal Detection |
Enables the internal OOB signal detector. OOB signal detection is used for PCIe and SATA. |
Table: PRBS Detector details the PRBS settings.
Table: Channel Bonding Setup shows the channel bonding options.
Table: Clock Correction Setup shows the clock correction options.