PCI Express, SATA, OOB, PRBS, Channel Bonding, and Clock Correction Selection - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

Page 5 of the Wizard (This Figure) allows you to configure the receiver for PCI Express and Serial ATA (SATA) features. In addition, configuration options for the RX out-of-band (OOB) signal, pseudo-random bitstream sequence (PRBS) detector, and channel bonding and clock correction settings are provided.

Figure 4-14:      PCIe, SATA, OOB, PRBS, Channel Bonding, and Clock Correction Selection—Page 5

X-Ref Target - Figure 4-14

pg168_viv_pcie.png

Table: Receiver Serial ATA Options details the receiver SATA configuration options.

Table 4-26:      Receiver Serial ATA Options

Options

Description

Enable PCI Express

Selecting this option enables certain operations specific to PCI Express, including enabling options for PCI Express powerdown modes and PCIe® channel bonding. This option should be activated whenever the transceiver is used for PCI Express.

SATA COM Sequence

Bursts

Integer value between 0 and 7 indicating the number of burst sequences to declare a COM match. This value defaults to 4, which is the burst count specified in the SATA specification for COMINIT, COMRESET, and COMWAKE.

Idles

Integer value between 0 and 7 indicating the number of idle sequences to declare a COM match. Each idle is an OOB signal with a length that matches COMINIT/COMRESET or COMWAKE.

Notes:

1.Options not used by the XAUI example are shaded.

Table: PCI Express and SATA Parameters details the receiver PCI Express configuration options.

Table 4-27:      PCI Express and SATA Parameters

Option

Description

Transition Time

To P2

Integer value between 0 and 65,535. Sets a counter to determine the transition time to the P2 power state for PCI Express. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] for details on determining the time value for each count.

The XAUI example does not require this feature and uses the default setting of 100.

From P2

Integer value between 0 and 65,535. Sets a counter to determine the transition time from the P2 power state for PCI Express. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] for details on determining the time value for each count.

The XAUI example does not require this feature and uses the default setting of 60.

To/From non-P2

Integer value between 0 and 65,535. Sets a counter to determine the transition time to or from power states other than P2 for PCI Express. See the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7] for details on determining the time value for each count.

The XAUI example does not require this feature and uses the default setting of 25.

Optional Ports

LOOPBACK

3-bit signal to enable the various data loopback modes for testing.

RXSTATUS

3-bit receiver status signal. The encoding of this signal is dependent on the setting of RXSTATUS encoding format.

RXVALID

Active-High, PCI Express RX OOB/beacon signal. Indicates symbol lock and valid data on RXDATA and RXCHARISK[3:0].

COMINITDET

Active-High initialization detection signal.

COMSASDET

Active-High detection signal for SATA.

COMWAKEDET

Active-High wake up detection signal.

TXCOMINIT

Transmit initialization port.

TXCOMSAS

OOB signal.

TXCOMWAKE

OOB signal.

COMFINISH

Completion of OOB.

TXDETECTRX

PIPE interface for PCI Express specification-compliant control signal. Activates the PCI Express receiver detection feature. Function depends on the state of TXPOWERDOWN, RXPOWERDOWN, TXELECIDLE, TXCHARDISPMODE, and TXCHARDISPVAL. This port is not available if RXSTATUS encoding format is set to SATA.

TXELECIDLE

Drives the transmitter to an electrical idle state (no differential voltage). In PCI Express mode this option is used for electrical idle modes. Function depends on the state of TXPOWERDOWN, RXPOWERDOWN, TXELECIDLE, TXCHARDISPMODE, and TXCHARDISPVAL.

PHYSTATUS

PCI Express receive detect support signal. Indicates completion of several PHY functions.

TXPOWERDOWN

Powerdown port for the transmitter.

RXPOWERDOWN

Powerdown port for the receiver.

Notes:

1.Options not used by the XAUI example are shaded.

Table: OOB Signal Detection shows the OOB signal detection options.

Table 4-28:      OOB Signal Detection

Option

Description

Use RX OOB Signal Detection

Enables the internal OOB signal detector. OOB signal detection is used for PCIe and SATA.

Table: PRBS Detector details the PRBS settings.

Table 4-29:      PRBS Detector

Option

Description

Use PRBS Detector

Enables the internal PRBS detector. This feature can be used by an application to implement a built-in self test.

Use Port TXPRBSSEL

Selects the PRBS Transmission control port.

Use Port TXPRBSFORCEERR

Enables the PRBS force error control port. This port controls the insertion of errors into the bitstream.

RXPRBSERR_LOOPBACK

Select this option to loopback RXPRBSERR bit to TXPRBSFORCEERR of the same transceiver.

Notes:

1.Options not used by the XAUI example are shaded.

Table: Channel Bonding Setup shows the channel bonding options.

Table 4-30:      Channel Bonding Setup

Option

Description

Use Channel Bonding

Enables receiver channel bonding logic using unique character sequences. When recognized, these sequences allow for adding or deleting characters in the receive buffer to byte-align multiple data transceivers.

Sequence Length

Select from the drop-down list the number of characters in the unique channel bonding sequence.

The XAUI example uses 1.

Sequence Max Skew

Select from the drop-down list the maximum skew in characters that can be handled by channel bonding. Must always be less than half the minimum distance between channel bonding sequences.

The XAUI example uses 7.

Use Two Channel Bonding Sequences

Activates the optional second channel bonding sequence. Detection of either sequence triggers channel bonding.

Notes:

1.Options not used by the XAUI example are shaded.

Table: Clock Correction Setup shows the clock correction options.

Table 4-31:      Clock Correction Setup

Option

Description

Use Clock Correction

Enables receiver clock correction logic using unique character sequences. When recognized, these sequences allow for adding or deleting characters in the receive buffer to prevent buffer underflow/overflow due to small differences in the transmit/receive clock frequencies.

Sequence Length

Select from the drop-down list the number of characters (subsequences) in the unique clock correction sequence.

The XAUI example uses 1.

PPM Offset

Indicates the PPM offset between the transmit and receive clocks.

Periodicity of the CC Sequence

Indicates the interval at which CC sequences are inserted in the data stream.

Use Two Clock Correction Sequences

Activates the optional second clock correction sequence. Detection of either sequence triggers clock correction.

Notes:

1.Options not used by the XAUI example are shaded.