The intent for the reset FSM included in the example design is to provide:
•An application example of an initialization FSM meeting the requirements described in 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7].
•An example of an initialization FSM that addresses industry challenges to initialize the GT transceivers in scenarios such as post FPGA-configuration and RX data interruption or replacement (such as cable plug or unplug).
The reset FSM is constantly being improvised to provide a robust initialization and reset scheme. The FSM is to demonstrate the right methodology and should not be mistaken as a specification.
The tx_startup_fsm is illustrated on the left side of This Figure.
Note: If RX and TX are combined in a core, only the TX FSM will reset the PLL. If RX-Only Core is generated, then RX FSM will reset the PLL.
The C/QPLL lock is monitored along with TXUSRCLK stability prior to TXRESETDONE. Buffer bypass logic for phase alignment is implemented if the TX buffer is disabled.
The rx_startup_fsm is also illustrated on the right side of This Figure. The C/QPLL lock, recovered clock stability, and RXUSRCLK are examined prior to RXRESETDONE followed by the buffer bypass logic for phase alignment. The FSM finally stays at the state that monitors data validity, which can be an 8B/10B error, frame sync error, or CRC from the user design until a user-defined error occurs.
The rx_startup_fsm can reset the RX side of the transceiver if data_valid is lost between receives (possibly due to cable pull up). This can be enabled by setting the port DONT_RESET_ON_DATA_ERROR. If DONT_RESET_ON_DATA_ERROR = 1'b0, the FSM auto resets if an error is detected.
|
S.No |
Port Name |
Clock Domain |
Description |
|---|---|---|---|
|
1 |
SOFT_RESET_TX_IN |
sysclk_in |
Active High reset to reset the TX Startup FSM and to start the TX initialization. |
|
2 |
SOFT_RESET_RX_IN |
sysclk_in |
Active High reset to reset the RX Startup FSM and to start the RX initialization. |
|
3 |
GT<n>_DATA_VALID_IN |
sysclk_in |
Indicates that data is valid on the RX side. |
|
4 |
GT<n>_TX_FSM_RESET_DONE_OUT |
sysclk_in |
Indicates TX initialization is complete. |
|
5 |
GT<n>_RX_FSM_RESET_DONE_OUT |
sysclk_in |
Indicates RX initialization is complete. |
|
6 |
DON’T_RESET_ON_DATA_ERROR_IN |
Asynchronous |
Used to auto-reset the RX side if an error is detected. If DONT_RESET_ON_DATA_ERROR = 1'b0, the FSM auto-resets when an error is detected. |
These are some assumptions and notes for the Example Reset FSM:
•A stable REFCLK is assumed to be present at all times.
•All resets are assumed to be in Sequential mode. The reset FSMs run on SYSCLK, which is the same as the DRPCLK. If the SYSCLK and DRPCLK are not the same in the user design, care should be taken to add the appropriate synchronizers.
•The example design engaged additional gates available such as PLLREFCLKLOST and Wait-time. Wait-time in use should not be regarded as the specification.
•RECCLK_STABLE is used as an indicator of RXOUTCLK (recovered clock) stability within a configured PPM offset from the reference clock (default 5000 ppm). The appropriate TDLOCK is used. See the Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics (DS183) [Ref 1].
•The example design defaults FRAME_CHECKER as data_valid. You can identify your data valid indicator and provide the necessary hysteresis on this signal to avoid a false indication of data_valid. Data valid is only used as an indicator to monitor the RX link. You need to customize the data valid indicator based on your system design.
•You can modify or re-invent an FSM to meet your specific system requirements while adhering to the guidelines in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 7].
•There might be other restrictions in answer records or errata.