The example design also demonstrates how to reset GTZ and enable the CTLE tuning for a given channel in an octal. It is essential to enable CTLE tuning to receive clean data on the serial interface of the GTZ transceiver in internal PMA loopback. The <Component_name>_pll_gtx_tx_rx_ctle.v module demonstrates an implementation of the procedure documented in the 7 Series FPGAs GTZ Transceivers User Guide (UG478) [Ref 12]. This module is instantiated once for each octal instantiation because it uses the DRP interface associated with an octal to make enables and monitor the CTLE tuning.
The interface for this module is shown in Table: CTLE Tuning Module Ports.
Table 5-16: CTLE Tuning Module Ports
|
Ports
|
Direction
|
Description
|
|
FIBRESET
|
OUTPUT
|
Resets the RX FIB part of every GTZ in an octal.
|
|
FSM_DONE
|
OUTPUT
|
Indicates that TX and RX are out of reset and GTZ is ready to use.
|
|
RD
|
OUTPUT
|
The DRP interface port to be connected to the corresponding signal on the octal.
|
|
WR
|
OUTPUT
|
The DRP interface port to be connected to the corresponding signal on the octal.
|
|
DRPADDR_O
|
OUTPUT
|
The DRP interface port to be connected to the corresponding signal on the octal.
|
|
DATA
|
OUTPUT
|
The DRP interface port to be connected to the corresponding signal on the octal.
|
|
TXEN
|
OUTPUT
|
Should be connected to TXEN of each GTZ. It Enable the TX SerDes for the lane.
|
|
RXEN
|
OUTPUT
|
Should be connected to RXEN of each GTZ. It Enable the RX SerDes for the lane.
|
|
GTZTXRESET
|
OUTPUT
|
Resets both FIB and SerDes on TX side.
|
|
GTZRXRESET
|
OUTPUT
|
Resets both FIB and SerDes on RX side.
|
|
PLLRECAL
|
OUTPUT
|
Recalibrates the PLL if either TXEN or RXEN is asserted
|
|
CLK
|
INPUT
|
Clk to the module.
|
|
RESET
|
INPUT
|
Resets the entire state machine.
|
|
TXRESETDONE
|
INPUT
|
Indicates that TX has come out of reset and is ready to use.
|
|
RXRESETDONE
|
INPUT
|
Indicates that RX has come out of reset and is ready to use.
|
|
TXRDY
|
INPUT
|
Indicates that TX PLL is locked.
|
|
RXRDY
|
INPUT
|
Indicates that RX PLL is locked.
|
|
TUNING_ADDR1
|
INPUT
|
The address for checking the status of CTLE tuning.
|
|
TUNING_ADDR2
|
INPUT
|
The address for setting the CTLE tuning mode and enabling it.
|
|
DRPRDY
|
INPUT
|
The DRP interface port to be connected to the corresponding signal on the octal.
|
|
DRPDO
|
INPUT
|
The DRP interface port to be connected to the corresponding signal on the octal.
|
|
REDO_CTLE_TUNING
|
INPUT
|
When enabled, the tuning enable FSM re-enables the CTLE tuning.
|
|
DISABLE_TUNING
|
INPUT
|
Disables tuning for that lane.
|
|
REDO_RXRESET_CTLE_TUNING
|
INPUT
|
When enabled, the tuning enable FSM re-enables the RXRESET and also CTLE tuning.
|
|
REDO_PLL_RESET
|
INPUT
|
When enabled, only PLL reset is performed.
|
The <component_name>_pll_gtz_tx_rx_ctle.v module performs the necessary reset sequence for GTZ and also CTLE tuning. The FSM_DONE signal indicates that the transceiver is out of reset and CTLE tuning is done.
To tune individual lanes, you can enable the REDO_CTLE_TUNING port for the particular lane. In the <Component_name>_init.v file, change the oct<octal>_lane_select_i signal to the particular lane.
This Figure and This Figure show the Reset and CTLE tuning enable state machine.
Figure 5-3: Reset and CTLE Tuning Enable State Machine
|
X-Ref Target - Figure 5-3
|
Figure 5-4: Continued Reset and CTLE Tuning Enable State Machine
|
X-Ref Target - Figure 5-4
|
