Revision History - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

The following table shows the revision history for this document.

Date

Version

Revision

05/19/2022

3.6

General updates.

11/30/2016

3.6

Chapter 2: Added port direction and clock domain information.

09/30/2015

3.6

Removed the GREFCLK reference clock source option, and added further information related to REFCLK0 and REFCLK1.

Example Design chapter:

°Changed example design to include Reset with CTLE tuning.

°Added new CTLE Tuning Module Ports and details.

°Added new CTLE Tuning Enable State Machine diagrams.

°Added steps for using the example design in hardware.

°Updated the Known Limitations of the GTZ Wizard section.

04/01/2015

3.5

Updated for Wizard v3.5 and Vivado Design Suite 2015.1.

Added additional ports to the Optional Ports table.

Added more details about resetting the Finite State Machine (FSM) in the Example Design chapter.

10/01/2014

3.4

Wizard 3.4 release. Updated to Vivado Design Suite 2014.3 throughout. Removed support for PCI Express throughout.

IP Facts: Updated Example Design and Test Bench rows in LogiCORE IP Facts Table.

Chapter 1: Added SATA: 6.0 to list of supported standards for GTX and GTP transceivers in Feature Summary. Updated Unsupported Features.

Chapter 4: Updated Figure 4-1, and Figure 4-5 to Figure 4-15.

Appendix B: Updated Figure B-4 and Figure B-5.

06/04/2014

3.3

Wizard 3.3 release. Updated to Vivado Design Suite 2014.2 throughout.

Chapter 4: Updated Figure 4-1, and Figure 4-5 to Figure 4-16.

04/02/2014

3.2

Wizard 3.2 release. Updated to Vivado Design Suite 2014.1 throughout.

Added Zynq SoCs to LogiCORE IP Facts Table.

Chapter 2: Added I/O column to Table 2-2, Table 2-3, and Table 2-4. In Table 2-5, updated column heading to SRIO Gen2. Updated DRP port in Table 2-6.

Chapter 4: Updated Figure 4-1, and Figure 4-3 to Figure 4-16. Removed Figure 4-5: “Starting a New Project,” Figure 4-6: “Locating the Transceiver Wizard,” and Figure 4-7: “Locating the Transceiver Wizard (Vivado Tools).” Updated Configuring and Generating the Wrapper.

Appendix B: Updated Overview of Major Changes. Removed Figure B-1: Include Shared Logic in Core, and Figure B-2: Include Shared Logic in Example Design.

Appendix C: Updated Debugging Using Embedded BERT.

12/18/2013

3.1

Wizard 3.1 release. Updated to Vivado Design Suite 2013.4 throughout.

Chapter 1: Updated GTZ support list in Feature Summary.

Chapter 2: In Table 2-1, replaced DRP_CLK_IN with DRP_CLK_IN_P/DRP_CLK_IN_N and updated description. Added Table 2-6 and Table 2-7.

Chapter 3: In Table 3-1, replaced DRPCLK with DRP_CLK_IN_P/DRP_CLK_IN_N and updated description.

Chapter 4: Updated Figure 4-1, and Figure 4-6 to Figure 4-16.

Chapter 5: Updated XDC file output in Example Design.

Appendix B: Updated Figure B-1, Figure B-2, and Figure B-4.

Appendix C: Updated filename in Hardware Debug. Added bullet after Figure C-3. Added step 3 to GTX Transceiver Validation. Updated Figure C-7.

10/02/2013

3.0

Initial release of this core as a product guide. This new guide is based on UG769.