1.Generate one 7 series FPGA transceiver core with the include Shared Logic in core option (referred to as the master core throughout this document), and generate one more 7 series FPGA transceiver core with the include Shared Logic in example design option (referred to as the slave core throughout this document). The common module can be shared across four transceivers in a Quad. The cores can be connected together with the “shareable” outputs from the master connected to the slave cores. Name the master core gtwizard_master and the slave core gtwizard_slave.
2.Generate the example design for the master core gtwizard_master. This produces an example design with a pattern generator module and a checker module.
3.Generate the example design for the slave cores. This produces an example design containing a core support layer of the slave core gtwizard_slave.
4.Open the <component_name>_support.v file of the slave cores and copy the <component_name>.v of the slave cores instance and paste it twice into the core support level of the master core gtwizard_master. Close the slave example project.
5.You will now need to further edit the master example design and core support level as follows:
a.Bring all the ports of the slave core instances to the core support level of the master core except txusrclk, txusrclk2, rxusrclk, rxusrclk2, drpclk, qplloutrefclk, qplloutclk (for GTX/GTH transceivers) and pll0outrefclk, pll0outclk, pll1outrefclk, pll1outclk (for GTP transceivers) and soft_reset.
b.Connect txusrclk, txusrclk2, rxusrclk, rxusrclk2, drpclk, qplloutrefclk, and qplloutclk soft_reset of slave core instances to the same source as the master core instance.
c.Replicate the pattern generator and pattern checker instance in the example design of the master core and connect the signals of the slave cores that are brought to the core support level.
d.Create unique signals for the DRP interfaces on the slave cores and connect them in the same way as is done for the master core.
Suggestion: use s1_drp_* for slave 1 and s2_drp_* for slave 2
e.Create unique signals for the tx/rxresetdone_out ports for the slaves and AND all slave txresetdone_out together with the master txresetdone_out output from the master. Similarly, AND all slave rxresetdone_out together with the master rxresetdone_out output from the master. A unique signal should be created for the master resetdone_out ports m_txresetdone_out and m_rxresetdone_out to feed out to the example design resetdone_out port.
Verilog example:
assign txresetdone_out = m_txresetdone_out && s1_txresetdone_out && s2_txresetdone_out;
assign rxresetdone_out = m_rxresetdone_out && s1_rxresetdone_out && s2_rxresetdone_out;
f.In the module declaration for the example design, add new ports TXN_S1, TXP_S1, RXN_S1, RXP_S1, TXN_S2, TXP_S2, RXN_S2, and RXP_S2 for the slave designs and connect them to the TXP_OUT, TXN_OUT, RXP_IN, and RXN_IN ports of the corresponding slave cores instances in the core support level.