Signal Changes - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

At the individual transceiver wrapper level:

Extra transceiver debug ports required for the protocol support have been brought out. For details on the extra ports, refer to Table: Transceiver Control and Status Interface.

At the multi-transceiver wrapper level:

Extra transceiver debug ports required for the protocol support have been brought out as mentioned above, as well as extra ports from the GTXE2/GTHE2/GTPE2_COMMON modules that are required to be connected to the GTXE2/GTHE2/GTPE2_CHANNEL.

For GTX/GTH transceivers:

qplloutclk

qplloutrefclk

For GTP transceivers:

pll0outclk

pll0outrefclk

pll1outclk

pll1outrefclk

At the Init wrapper level:

Extra transceiver debug ports required for the protocol support have been brought out, as well as extra ports from the GTXE2/GTHE2/GTPE2_COMMON modules that are required to be connected to the GTXE2/GTHE2/GTPE2_CHANNEL as mentioned above and the PLL lock signals that will be used by the TX/RX start up FSMs.

For GTX/GTH transceivers:

qplllock

For GTP transceivers:

pll0lock

pll1lock