Structure of the Transceiver Wrapper, Example Design, and Test Bench - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

This Figure shows the relationship of the transceiver wrapper, example design, and test bench files generated by the Wizard. For details, see Example Design Description for GTX, GTH, and GTP Transceivers.

Figure 1-3:      Structure of the Transceiver Wrapper, Example Design, and Test Bench

X-Ref Target - Figure 1-3

pg168_c1_03.jpg

The following files are generated by the Wizard to illustrate the components needed to simulate the configured transceiver:

Transceiver wrapper, which includes:

°Specific serial transceiver configuration parameters set using the Wizard.

°Transceiver primitive selected using the Wizard.

Example design demonstrating the modules required to simulate the wrapper. These include:

°FRAME_GEN module: Generates a user-definable data stream for simulation analysis.

°FRAME_CHECK module: Tests for correct transmission of data stream for simulation analysis.

Test bench: Top-level test bench demonstrating how to stimulate the design.