TX/RX Buffer Testing - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

In the TX path, a TX FIFO is available to control the data flow between the PCS and PMA clock domain. Similarly, the elastic buffer is available in the RX path. In the RX path, the datapath is tested with the buffer and in bypass mode.