TX/RX USERCLK Testing - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

This tests all possible combinations of the TX and RX user clock source (Table: Combinations of User Clock Source).

Table C-12:      Combinations of User Clock Source

TXUSRCLK Source

RXUSRCLK Source

TXOUTCLK

TXOUTCLK

TXOUTCLK

RXOUTCLK

RXOUTCLK

TXOUTCLK

RXOUTCLK

RXOUTCLK