Transceiver Core Debug - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

To provide additional control and debug visibility of the transceivers based on the protocol template selected from the GUI, the 7 series FPGAs Transceivers Wizard core is provided with debug ports required for transceiver core debug that are useful when debugging transceiver links. For more information on transceiver debug ports, refer to Table: Transceiver Control and Status Interface. These control and debug ports allow Wizard users to fine tune the transceiver’s TX driver and RX equalization, in addition to other functions such as the ability to send/detect PRBS patterns. These ports allow you to tune the transceiver to your particular link.