Using Vivado Design Suite Debug Feature with the Wizard - 3.6 English

7 Series FPGAs Transceivers Wizard (PG168)

Document ID
PG168
Release Date
2022-05-19
Version
3.6 English

The Vivado Design Suite debug feature ILA and VIO cores aid in debugging and validating the design in the board. To assist with debugging, these cores are provided with the 7 series FPGAs Transceivers Wizard wrapper, which is enabled by setting USE_CHIPSCOPE to 1 in the <component_name>_exdes.v[hd] file.