Wizard Validation Scope - 3.6 English

As shown in This Figure, a GTX transceiver channel in the 7 series FPGA has two main blocks: transmitter and receiver. The PMA of each channel is configurable through attributes and DRP configuration whereas different submodules of PCS are configurable through ports and attributes. The validation of the Wizard will mostly focus on:

•Datapath Testing

•Different PLL Testing

•Loopback Mode Testing

•PRBS Mode Testing

•TX/RX Buffer Testing

•REFCLK Testing

•Powerdown Testing

•TX/RX Rate-change Testing

•TX/RX Polarity Testing

•TX/RX Electrical Idle Testing

•Encoding and Decoding Testing

•Comma Detection Testing

•Comma Alignment Testing

•TX/RX OOB Testing

•TX/RX PCIe Beacon Testing

•PCIe Receiver Detection Testing

•Channel-bond Testing

•Clock-correction Testing

•TX/RX USERCLK Testing

•Reset Testing

As shown in This Figure, two FPGAs on different boards are connected through a BullsEye cable. This setup replicates a real scenario of how the SerDes usually talk to each other. Using this board-to-board setup, datapath testing can be done in five different ways as discussed in Loopback Configuration Testing.

Vivado Design Suite debug feature is used to debug and trigger a special case to test using the same bit image. For example, to configure a specific loopback mode you can use the VIO core and pass a required value to configure a particular case. Similarly, the Vivado Design Suite debug feature helps to test different features by enabling and disabling them using both ILA and VIO cores.