This directory contains shared logic resource files.
|
Name |
Description |
|---|---|
|
<component_name>_support.v[hd] |
Core support layer of the 7 series FPGA transceiver design. |
|
<component_name>_gt_usrclk_source.v[hd] |
Transceiver user clock module that generates clocking signals for transceivers and the user logic. |
|
<component_name>_common.v[hd] |
This file instantiates the GTXE2_COMMON or GTXE2_COMMON primitive, which is shared across respective multiple transceiver cores. |
|
<component_name>_common_reset.v[hd] |
This file generates the reset circuitry that is used as a core reset for the 7 series FPGAs Transceivers Wizard core. |