This section includes information about using AMD tools to customize and generate the core in the Vivado Design Suite. The SEM controller is device dependent and a device that supports SEM IP must be chosen. To customize and generate the core, locate the IP core in the Vivado IP catalog at FPGA Features and Design > Soft Error Mitigation > UltraScale Soft Error Mitigation and click it once to select it. Important information regarding the solution is displayed in the Details pane of the Project Manager window. Review this information before proceeding.
Double-click the IP core in the Vivado IP catalog to open the customization dialog box, shown in Figure 1.
The SEM controller IP customization Vivado IDE is organized in three tabs:
- Provides customization options for the elementary SEU mitigation features including IP mode, target clock period, and structural options for the configuration primitives and helper blocks.
- Advanced Mitigation
- Provides customization options for more complex SEU mitigation features including error classification.
- Provides a summary of the selected IP configuration specified in the Basic and Advanced Mitigation tabs. Review the selected configuration before generating the IP.
Review each of the available options, and modify them as desired so that the SEM controller solution meets the requirements of the larger project into which it is integrated. The following subsections discuss the options in detail to serve as a guide.