Error Detection Latency

Error Detection Latency - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID

PG187

Release Date

2023-11-08

Version

3.1 English

Error detection latency is the major component of the total error mitigation latency. Error detection latency is a function of the FPGA size (frame count) and the solution clock frequency. It is also a function of the type of error and the relative position of the error with respect to the position of the silicon readback process.

The following tables illustrate IP error detection time. These numbers are only applicable when the IP is in the mitigation mode (detect and correct), detect mode, and detect only state.

Table 1. Maximum IP Error Detection Times at ICAP F_Max for UltraScale Devices
Device		Detection Time at ICAP F_Max (ms)
UltraScale	XCKU035	22
	XCKU040¹	22
	XCKU060	30
	XCKU085	30
	XCKU095	41
	XCKU115	30
	XCVU065	30
	XCVU080	41
	XCVU095	41
	XCVU125	30
	XCVU160	30
	XCVU190	30
	XCVU440	58
Measured in hardware. Data for other devices in this architecture are extrapolated based on this measurement.

Table 2. Maximum IP Error Detection Times at ICAP F_Max for UltraScale+ Devices
Device		Detection Time at ICAP F_Max (ms)
UltraScale+	XCKU3P	19
	XCKU5P	19
	XCKU9P	28
	XCKU11P	29
	XCKU13P	33
	XCKU15P	42
	XCVU3P¹	32
	XCVU5P	52
	XCVU7P	52
	XCVU9P¹	52
	XCVU11P	57
	XCVU13P	57
	XCVU27P	57
	XCVU29P	57
	XCVU31P	37
	XCVU33P	37
	XCVU35P	57
	XCVU37P	57
	XCVU45P	57
	XCVU47P	57
	XCZU1	9
	XCZU2	9
	XCZU3	9
	XCZU4	13
	XCZU5	13
	XCZU6	28
	XCZU7	26
	XCZU9	28
	XCZU11	29
	XCZU15	33
	XCZU17	42
	XCZU19	42
UltraScale+ (Continued)	XCZU21DR	40
	XCZU25DR	40
	XCZU27DR	40
	XCZU28DR	40
	XCZU29DR	40
	XCZU46DR	40
	XCZU47DR	40
	XCZU48DR	40
	XCZU49DR	40
	U55N	57
	U55C	57
	XCVU57P	57
	XCVU19P	57
	XCVU15P	57
	XCVU23P	37
	XCK26	13
	XCUX35	37
	XCAU25P	19
	XCAU20P	19
	XCAU15P	19
	XCAU10P	19
Measured in hardware. Data for other devices in this architecture are extrapolated based on this measurement.

The IP error detection time for the target device, at the actual frequency of operation, can be estimated using data from the previous tables and the following equation.

Figure 1. Detection Latency

The error detection latency can be bounded as follows:

Maximum error detection latency for detection by ECC is DetectionTime_ACTUAL
Absolute maximum error detection latency for detection by CRC alone is 2.0 × DetectionTime_ACTUAL

In the case of multi-bit errors caused by a single SEU event that spread across four adjacent frames, the SEM controller algorithm has been optimized to reduce the detection time of the errors in the subsequent frames to the minimum. This algorithm enables the controller to detect and correct up to 16-bit errors across four adjacent frames in a single pass. The worst case accumulative detection time for multi-bit errors is to multiply the number of single-bit error with the worst case detection time for a single-bit error.

The error detection latency when using the Diagnostic Scan feature is significantly larger than the mitigation mode, detect mode, or detect only scan and is dependent on the device, number of errors detected, and the actual frequency of operation.

For example, if a Diagnostic Scan is performed on a KU040 device that has three errors resident in its configuration memory using a 90 MHz clock, it takes 70 seconds to scan and report all errors.