The solution behaviors are based on the processing of FPGA configuration memory frames. Single-bit errors always reside in a single frame. Generally, an N -bit error can be present in several ways, ranging from one frame containing all bit errors, to N frames each containing 1-bit error. When multiple frames are affected by an error, the sequence of detection, correction, and classification is repeated for each affected frame.
The solution properly mitigates an arbitrary workload of errors. The error mitigation latency estimation of an arbitrary workload is complex. This section focuses on the common case involving a single frame, but provides insight into the controller behavior to aid in understanding other scenarios.